Conference and Journal Publications

Toward Compact Planar Circuits for Atomic-Scale Computing: A Hybrid Crossing Elimination Flow

Published in IEEE International Conference on Nanotechnology (IEEE NANO), 2026

The growing computational demands of artificial intelligence challenge the continued scaling of conventional CMOS technology, motivating the exploration of alternative paradigms such as Atomic-Scale Computing. Among potential implementations, Field-Coupled Nanocomputing (FCN) is a promising candidate that transmits information through electric or magnetic field interactions rather than current flow, enabling extremely dense circuits with potentially terahertz operating frequencies. However, FCN circuits are implemented on a single physical layer where logic gates and interconnects share the same structures. Consequently, signal crossings pose a major challenge, since proposed wire-crossing structures are not sufficiently reliable for physically realizable layouts. Previous work addresses this by performing planarization—i.e., eliminating crossings—during logic synthesis via node duplication to provide planar networks for placement and routing. However, this approach suffers from poor scalability and neglects necessary preprocessing steps required for valid FCN logic networks. In this work, we propose a planar FCN synthesis flow that improves the interaction between preprocessing steps for FCN logic networks and planarization. Furthermore, we introduce a hybrid crossing elimination strategy that resolves intersections through either node duplication or equivalent logical structures that emulate signal crossings, thereby bypassing the need for physical crossing gates. Experimental results demonstrate significant reductions in network size, achieving an average reduction of 34.65 %, and up to 97.71 % for circuits where node duplication exhibits particularly poor scalability, enabling more compact planar circuits suitable for subsequent placement and routing. Read more

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Operational Domain Sketching for Silicon Dangling Bond Logic

Published in IEEE International Conference on Nanotechnology (IEEE NANO), 2026

Silicon Dangling Bond (SiDB) logic is an innovative post-CMOS computing technology that operates at the atomic scale, delivering unmatched energy efficiency. However, despite its transformative potential, SiDB logic encounters a significant challenge: its sensitivity to material imperfections and variations in the physical properties of the H-Si(100)-2×1 surface on which it is fabricated, which can render gates non-operational. To address this sensitivity, the concept of the Operational Domain has gained traction in the literature—a range of physical parameter combinations that ensure reliable gate operation. Physical simulations are a standard approach to determining whether a gate is operational for given physical parameters. However, evaluating numerous parameter points can result in exponential scaling. While existing methods aim to reduce the number of simulator calls, they still rely on physical simulations, leading to inconvenient runtime. Motivated by that, we propose an algorithm that efficiently identifies non-operational parameter points without relying on physical simulations, while assuming operability for the remaining points. Since this approach might yield false positives, we call the resulting plot the Operational Domain Sketch, an approximation of the operational domain. Experimental analysis shows that the sketch can be obtained with runtime improvements of up to 365x compared to the state of the art, providing a fast method for determining the robustness of SiDB logic. This, in turn, facilitates the design of robust gates and enables reliable SiDB circuits. Read more

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Minimizing Area and Delay in Planar Physical Design for Field-coupled Nanocomputing

Published in IEEE International Conference on Nanotechnology (IEEE NANO), 2026

Field-coupled Nanocomputing (FCN) is a promising post-CMOS technology that transmits information via electric or magnetic fields rather than current flow. It uses nanoscale cells to implement logic gates and interconnects, enabling minimal circuit footprints and high computational density. These properties make FCN well-suited for future high-performance applications such as artificial intelligence and scientific computing. Unlike CMOS, FCN circuits are constrained to a single physical layer, requiring logic and interconnects to coexist in the same plane. In FCN layouts, wire crossings are commonly used to route intersecting signals. However, experimental and simulation studies have shown that such crossings degrade signal stability and reliability, making them unsuitable for practical FCN designs. As a result, planar layouts that completely avoid wire crossings are a strict requirement for reliable circuit implementation. This work presents a placement and routing algorithm that generates fully planar FCN layouts while optimizing both area and delay. In contrast to the current state-of-the-art planar physical design flow, which relies on greedy heuristics, our method performs placement and routing in a level-by-level manner, effectively minimizing wiring overhead within each level. Experimental results demonstrate that our approach achieves an average reduction of 21.09 % in layout area and 15.24 % in delay, providing a scalable and efficient solution for practical FCN circuit implementation. Read more

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Holistic Physical Design for Silicon Atomic Logic: Cramming More Components onto Clock Zones

Published in IEEE International Conference on Nanotechnology (IEEE NANO), 2026

Field-Coupled Nanocomputing (FCN) presents an exciting foundation for post-CMOS computing, and among its variants, Silicon Dangling Bond (SiDB) logic shows particular promise. Building on this technology, recent work has established an end-to-end design flow that synthesizes SiDB circuits directly from logic-level specifications. These circuits rely on an FCN clocking scheme to ensure directional and stable computation across sequences of logic gates. This clocking mechanism is indispensable: it actively nullifies parasitic interactions—or crosstalk—that arise when multiple gates are placed in close proximity, a fundamental concern in FCN-based circuits. However, a curious mismatch arises: while logic gates in SiDB can be implemented at the atomic scale, the metal pitches used to generate the clock signal remain relatively coarse. As a result, the nanoscopic SiDB logic gates must be artifically enlarged to fit one gate per clock zone, simply to interface with the clocking infrastructure. This approach, though functional, squanders the incredible density potential of atom-scale SiDB logic. To unlock that potential, we advocate for a holistic gate design methodology: crafting entire multi-gate assemblies that are small enough to fit into a single clock zone, while simultaneously mastering the delicate crosstalk interactions that such compactness entails. Yet, this compact design challenge gives rise to a monstrous design space. The number of possible combinations grows exponentially in the number of gates, with the number of distinct gate implementations as base—of which there are many thousands. Each candidate solution must be evaluated using physical simulation across all input combinations, which itself scales exponentially with the number of SiDBs in the design. As a result, design automation efforts to date have favored simpler, more sparse circuit topologies to preserve tractability—at the expense of logic density. In this work, we confront the challenge head-on. With an experimental evaluation, it is shown that the proposed methodology enables cramming significantly more logic into each clock zone of an SiDB circuit—advancing toward a truly holistic physical design flow for atomic-scale logic. Read more

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Design and Emulation Methodology for Atomic-Scale Systolic Arrays: An LLM Accelerator Case Study in Silicon DB Logic

Published in IEEE International Conference on Nanotechnology (IEEE NANO), 2026

LLMs increasingly strain memory bandwidth and compute resources as CMOS scaling plateaus. Emerging technologies such as atomic-scale computing with silicon dangling bonds (DBs) promise ultra-dense, low-power logic, yet application-level validation still lacks an executable, clock-driven hardware emulation framework. To address this gap, this work introduces a cross-layer flow that compiles register-transfer level (RTL) Verilog to a clock-driven, Verilator-based emulator exposed to Python via a co-simulation hardware abstraction layer (HAL). DB-aware RTL rules formalized in this work ensure representative emulation across the full systolic array, while allowing the same RTL to drive logic synthesis through fiction, a technology-specific EDA toolkit, to yield dot-accurate DB layouts. As a representative use case, a ternary DB matrix multiply unit (MXU) is designed in Verilog to target BitNet b1.58 acceleration, achieving up to 34× area reduction compared to prior DB MXUs and generating LLM tokens under cycle-accurate software emulation while matching GPU-baseline outputs. This bridges layout-centric studies and workload-driven evaluation, enabling reproducible, cross-layer accelerator design for this emerging technology. Read more

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BitPlanarNet: Learning-to-Layout Planar Gate Networks for Emerging Devices

Published in IEEE International Conference on Nanotechnology (IEEE NANO), 2026

Emerging planar computing platforms such as atomic-scale computing and silicon photonics combine gates and interconnects in a single 2D plane, making wiring and crossings dominant bottlenecks. This work reframes differentiable logic network training as one-pass synthesis: BitPlanarNet trains a strictly planar gate network that maps one-to-one to device primitives. Building on differentiable logic gate networks (DLGNs), each neuron selects a 2-input/2-output primitive and connects only to nearest neighbors, yielding a gate-level layout at discretization. It is demonstrated that this concept is physically viable by successfully fabricating a 33 × 25 nm2 representative learned dangling-bond logic layout on a hydrogen-passivated silicon surface using a scanning tunneling microscope. On image-classification tasks, BitPlanarNet achieves accuracy comparable to unconstrained DLGNs—remaining within approximately 1 percentage point on MNIST and 5 percentage points on CIFAR-10—while guaranteeing planar connectivity, providing a versatile methodology for translating learned tasks directly into realizable gate layouts on emerging planar technologies. Read more

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aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis

Published in International Workshop on Logic & Synthesis (IWLS), 2026

The rapid advancement of Machine Learning (ML) has demonstrated immense potential for logic synthesis, design-space exploration, and circuit optimization. In practice, however, researchers who want to combine these areas repeatedly face the same infrastructure problem: the surrounding ML and data-science ecosystem is centered on Python, whereas the core data structures and algorithms of logic synthesis are the product of decades of highly optimized C/C++ engineering. As a result, individual projects are often forced either to rebuild logic synthesis functionality from scratch in Python or to assemble brittle wrappers and file-based conversion pipelines around external tools. To address this recurring gap, this paper introduces aigverse, a unified open-source infrastructure project that brings mature logic synthesis capabilities into Python-first workflows without reimplementing them there. To this end, aigverse wraps high-performance C/C++ synthesis backends within an idiomatic Python interface and provides reusable support for circuit construction and manipulation, dataset generation, optimization and equivalence-checking flows, and export into graph and tensor representations for downstream data science and ML pipelines. In a case study comparing a pure-Python tensorization pipeline from the literature against aigverse, the latter achieves up to 17.2× faster end-to-end tensorization while reducing isolated framework hand-off overhead by three to four orders of magnitude depending on circuit size. In this way, aigverse is intended to provide for logic synthesis the kind of reusable, domain-aware software bridge that has already helped ML become effective in scientific fields such as medicine and chemistry without requiring those researchers to become application-domain experts. Read more

AIG2PT: A Generative Pre-trained Transformer for Unconditional And-Inverter Graph Synthesis

Published in International Workshop on Logic & Synthesis (IWLS), 2026

And-Inverter Graphs (AIGs) underpin modern logic synthesis and optimization, yet existing techniques explore only a narrow portion of the vast design space of valid circuit structures. To address this limitation, this paper introduces AIG2PT, a foundational building block toward structurally diverse, future function-aware, and equivalence-guided AIG generation. Inspired by advances in molecular generation, AIG2PT decouples structural synthesis from functional constraints, enabling the model to learn the syntax of valid, expressive, and structurally novel circuit topologies through unconditional generation. The approach adapts a Graph Generative Pre-trained Transformer (G2PT) with a domain-specific vocabulary and a topology-aware encoding. A systematic study of sampling strategies reveals tunable control over Validity, Uniqueness, and Novelty (V.U.N.) scores: 100 % structural validity and uniqueness with Diverse Beam Search, and over 60 % novelty with Multinomial Sampling. These results substantially outperform established deep learning-based graph-generation baselines, demonstrating that AIG2PT provides a robust foundation for future work in generative circuit design, conditional synthesis, and broad design space exploration. Read more

A Framework for Post-Mapping Feedback-Guided Selective Logic Transformations

Published in International Workshop on Logic & Synthesis (IWLS), 2026

Modern logic synthesis flows optimize proxy metrics, such as node count or depth, at the technology-independent level to indirectly improve area and delay. However, optimal values of proxy metrics do not necessarily translate to optimal post-mapping quality. With rising wafer costs at advanced technology nodes, area minimization becomes increasingly important, motivating the use of higher-effort optimization techniques. To address this development, we propose such a framework that leverages post-mapping information to guide technology-aware transformations, informed by feedback from the technology-mapping stage. Exemplarily applied to area-driven rewriting, the method achieves an average post-mapping area improvement of 0.72 % after a single iteration. The maximum gain is 6.3 %, with a strong effect size (r = 0.9167), at the cost of a runtime overhead of 274 %. Nevertheless, the method remains scalable even for very large circuits and is generically applicable to most optimization algorithms and objectives, such as post-mapping area and delay. However, these improvements do not consistently accumulate over multiple iterations. Nevertheless, the results demonstrate that, in the single-iteration case, feedback-guided transformations can improve technology-specific outcomes, even though they would be considered suboptimal by conventional proxy metrics. The proposed framework remains preliminary: it is at this moment still susceptible to becoming trapped in local minima and may exhibit instability due to uncertainties in selecting the correct transformation steps. While it is currently limited to discarding non-beneficial transformations exclusively, future work will explore enabling the discovery of new optimization opportunities to increase applicability. Read more

Practical HPCQC Integration with QDMI: A Real-Hardware Case Study with IQM Systems

Published in arXiv, 2026

Quantum computers are moving into HPC centers, and the main challenge is now integration rather than pure hardware access. Many current software paths still depend on vendor-specific adapter chains between user SDKs, schedulers, and backend APIs. This pattern makes operations more complex than necessary and slows the transition from pilots to production workflows. We present a practical integration path centered on the Quantum Device Management Interface (QDMI). Using IQM superconducting systems as a hardware case study, we implement an IQM-backed QDMI layer and connect it to two software layers that HPC centers working with quantum computers already care about: Slurm-based job execution and Qiskit-facing user workflows. The implementation is publicly available at github.com/iqm-finland/QDMI-on-IQM. The key message is simple: integrating quantum hardware into HPC does not have to be a bespoke engineering effort for each backend. Once the software-hardware boundary is standardized, large parts of the stack become reusable across providers and deployment styles. Our results do not claim that standardization eliminates all HPCQC challenges. They show that this specific boundary can already be standardized today in a way that is practical for users, operators, and vendors. Read more

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Exact Synthesis with Optimal Switching Activity

Published in Design, Automation and Test in Europe (DATE), 2026

Power consumption is a primary constraint in modern digital circuit design, with switching activity being a major contributor to dynamic power dissipation. While exact synthesis methods guarantee optimality for metrics such as gate count or delay, they typically do not directly target switching activity. This paper presents a novel SAT-based exact synthesis approach designed to minimize switching activity in combinational logic circuits. We extend existing SAT encodings for logic synthesis, incorporating new constraints and variables to model and constrain the switching behavior of the circuit. Different SAT encoding strategies, including BDD-based approaches for handling cardinality constraints, as well as various search algorithms, are explored. Experimental results on NPN benchmark functions demonstrate the effectiveness of the proposed method in identifying circuits with, on average, 6.7 % (over 30 % in the best case) reduced switching activity compared to traditional exact synthesis techniques, often achieving this reduction with no or minimal area overhead. While runtime remains challenging, this work establishes a foundation for power-aware exact synthesis. Read more

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Mastering the Exponential Complexity of Exact Physical Simulation of Silicon Dangling Bonds

Published in Asia and South Pacific Design Automation Conference (ASP-DAC), 2026

Silicon Dangling Bond (SiDB) logic is a promising technology for energy-efficient computation, supported by significant advancements in manufacturing and design automation. However, physical simulation, essential for accurately predicting the behavior of SiDB logic prior to costly manufacturing, lags behind these developments. In particular, exact physical simulation, which scales exponentially with base 3, remains infeasible for larger SiDB assemblies, limiting its utility to small structures such as single gates. This computational bottleneck slows progress in SiDB technology and hinders the establishment of reliable ground truths for heuristic approaches. To address the challenge, this work presents a novel methodology for exact SiDB simulation that restructures the exponential search space according to a hierarchical clustering. The hierarchy structure enables a systematic pruning of the search space at its different levels: it provides an ordering of interactions between clusters of SiDBs to facilitate efficacious exploitation of dynamically-inferred problem-specific constraints—like solving a Sudoku. Experimental results demonstrate that the effective exponential base can be lowered to approximately 1.3, enabling, for the first time, the exact physical simulation of entire multi-gate SiDB circuits in minutes that would take the state of the art millions of years to compute. This breakthrough establishes a robust ground truth for SiDB logic validation, marking a pivotal step toward scalable, energy-efficient, and atomic-scale computing. Read more

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RTL-to-Atoms Synthesis of a Machine Learning Accelerator on Atomic-Scale Computers

Published in IEEE Transactions on Nanotechnology (TNANO), 2026

As CMOS scaling slows and AI demand soars, atomic-scale platforms such as quantum-dot logic based on silicon dangling bonds (SiDBs) offer a promising path toward energy-efficient computation, yet practical design flows from register-transfer level (RTL) specifications to manufacturable layouts remain limited. This work presents an RTL-to-atoms synthesis framework for a quantized matrix multiply unit targeting SiDB-based field-coupled nanocomputing (FCN). Building on recent advances in SiDB-aware electronic design automation (EDA), the framework combines a hierarchical, parameterized RTL architecture with platform-optimized arithmetic logic units, reducing the synthesized logic core of processing elements by about 15 % compared to prior flows. Key improvements were also made to the synthesis workflow to better optimize for SiDB logic and incorporate figure-of-merit awareness, which together ensure that the synthesized layouts achieve favorable area scaling and throughput while balancing operational robustness. Evaluations across multiple bit-widths show substantial footprint reductions for configurations within the tractable range of the latest placement-and-routing algorithms while preserving testbench-validated correctness from RTL to dot-accurate SiDB layouts, thereby establishing a reproducible benchmark for EDA on atomic-scale computing. This represents a significant milestone, bridging manually intensive workflows with scalable, automated methodologies, providing a valuable foundation for future design efforts for SiDB-based accelerators. Read more

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Bridging the Gap Between Molecular FCN and Design Automation with SIM(7)-MolPDK: A Physically Simulated Standard-Cell Library

Published in IEEE Latin American Conference on Nanotechnology (IEEE LANANO), 2025

As CMOS technology approaches its physical and economic limits, alternative computing paradigms are being explored to overcome scaling, power, and manufacturing challenges. Field-Coupled Nanocomputing (FCN) is a promising post-CMOS approach that transmits information via electrostatic interactions rather than current flow. The molecular implementation of FCN—Molecular Field-Coupled Nanocomputing (MolFCN)—follows the Quantum-dot Cellular Automata (QCA) paradigm and offers room-temperature operation, ultra-high logic density, and ultra-low energy consumption. Recent advances in molecular device characterization and simulation make MolFCN circuit design more feasible than ever. However, most existing MolFCN circuits are manually designed under simplified assumptions, limiting their physical realism and scalability. While automated FCN design frameworks exist, they require verified Standard-Cell Libraries (SCLs), which are currently unavailable for molecular implementations. This work introduces SIM(7)-MolPDK, the first fully simulated MolFCN standard-cell library, enabling integration into an automatic FCN design framework. For the first time, physically realistic MolFCN circuits are synthesized automatically and validated through physical-level simulations, bridging the gap between molecular device research and design automation. Read more

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Graph-Oriented Layout Design for Field-coupled Nanocomputing via Parallel Multi-Objective Search Space Exploration

Published in IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), 2025

Field-coupled Nanocomputing (FCN) is a post-CMOS paradigm in which information propagates through near-field interactions rather than charge flow, enabling ultra-low-power, high-density logic. Translating netlists into manufacturable, cell-level layouts therefore becomes a pivotal challenge. Existing FCN physical design tools optimize only a single cost metric, typically footprint or runtime. As a result, designers must choose between exponentially slow exact solvers and fast yet area-intensive heuristics. We present the first FCN physical design engine that closes this gap by introducing configurable effort modes. These modes let users trade runtime for solution quality while simultaneously optimizing any discretionary objective, e. g. area, wire segments, crossings, or delay, thereby integrating data from physical simulation and manufacturing constraints. Our open-source implementation, released as part of the Munich Nanotech Toolkit, generates layouts for circuits that defeat state-of-the-art exact solvers. On such benchmarks, it shrinks footprint by an average of 73.07 %, reduces crossings by 19.10 %, and cuts wire segments by 54.47 % relative to a leading heuristic baseline. Even after post-layout optimization of the baseline, our approach still achieves mean gains of 25.99 % in area, 37.82 % in crossings, and 25.96 % in wire segments. These results establish the proposed engine as a compelling solution for highly optimized, large-scale standard-cell FCN design. Read more

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QuickCell: Fast Automatic Design of Standard Cells for Silicon Dangling Bond Logic

Published in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2025

In recent years, Silicon Dangling Bond (SiDB) logic has emerged as a promising beyond-CMOS technology due to its integration density and operating frequency. This advancement is driving the development of comprehensive design automation workflows, including physical simulators and gate design tools. Unlike conventional circuit technology, where logic is implemented through transistors, SiDB logic utilizes quantum dots with variable charge states. By strategically arranging these dots, standard logic functions like OR, AND, NAND, etc. can be implemented, which are usually provided as Standard Cells in design processes. However, finding such arrangements that implement a given Boolean function is a tremendously complex task that involves considering numerous candidates and verifying them through computationally expensive physical simulation. Hence, the automatic obtainment of SiDB logic layouts is thus far limited to simple 2-input functions only—which already require substantial computation resources. In contrast, conventional physical design algorithms for VLSI have long transitioned from single-gate considerations to multi-input standard cells. To address this challenge, this paper proposes QuickCell: A fast algorithm for automatic standard cell design for SiDB logic that uses dedicated search space pruning techniques. In an extensive experimental evaluation, it is demonstrated that combining these pruning techniques yields 1) a drastic reduction of the search space amounting to up to six orders of magnitude, 2) a corresponding decrease of the runtime by up to a factor of 91, 3) the capability to handle more complex functionality, as, e. g., utilized in standard cells, for the first time, significantly narrowing the gap between SiDB logic and conventional CMOS design paradigms, and 4) a significant speedup compared to physical simulation (up to a factor of 10 000), with near independence from the number of I/O pins when determining the non-operationality of a given layout. This efficiency makes these techniques—and by extension QuickCell—a powerful enabler for the design of complex standard cells. Read more

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MNT Designer: A Comprehensive Design Tool for Field-coupled Nanocomputing

Published in IEEE International Conference on Nanotechnology, 2025

Field-coupled Nanocomputing (FCN) is a class of post-CMOS technologies that operate at the nanoscale without relying on electrical current. Its potential was recently demonstrated by the fabrication of a fully functional OR gate occupying less than 30 nm2, using Silicon Dangling Bonds (SiDBs). A key step toward commercializing FCN is the development of software tools capable of automatically generating fabrication-ready, cell-level layouts. In this work, we present a novel, GUI-based tool that spans the complete design flow-from Verilog to atoms-including physical design algorithms, post-layout optimization, verification, and gate design. The tool is released as open-source at https://github.com/cda-tum/mnt-designer and is also available as a pip package. Read more

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Building a Machine Learning Accelerator with Silicon Dangling Bonds: From Verilog to Quantum Dot Layout

Published in IEEE International Conference on Nanotechnology, 2025

This work won the Best Student Paper Award at IEEE NANO 2025. Read more

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A Fully Planar Approach to Field-coupled Nanocomputing: Scalable Placement and Routing Without Wire Crossings

Published in IEEE International Conference on Nanotechnology, 2025

Field-coupled Nanocomputing (FCN) is a class of promising post-CMOS technologies that transmit information through electric or magnetic fields instead of current flow. They utilize basic building blocks called cells, which can form gates that implement Boolean functions. However, the design constraints for FCN circuits differ significantly from those for CMOS. One major challenge is that wires in FCN have to be realized as gates, i. e., they are constructed from cells and incur the same costs as gates. Additionally, all FCN technologies are fabricated on a single layer, e. g., a silicon surface, requiring all elements-gates and wires-to be placed within that same layer. Consequently, FCN employs special gates, called wire crossings, to enable signals to cross. While existing wire-crossing implementations are complex and were previously considered costly, initial efforts have aimed at minimizing their use. However, recent physical simulations and experiments on a quantum annealing platform have shown that currently used wire crossings in FCN significantly compromise signal stability, to the extent that circuits cannot function reliably. This work addresses that issue by introducing the first placement and routing algorithm that produces fully planar FCN circuits, eliminating the need for all wire crossings. For a comparative evaluation, a state-of-the-art placement and routing algorithm was also modified to enforce planarity. However, our proposed algorithm is more scalable and can handle inputs with up to 149k gates, enabling it to process circuits that are 182x more complex than those handled by the modified state-of-the-art algorithm. Read more

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The Operational Domain Explorer: A Comprehensive Framework to Unveil the Thermal Landscape of Silicon Dangling Bond Logic Beyond Conventional Operability

Published in IEEE International Conference on Nanotechnology, 2025

As Silicon Dangling Bond (SiDB) logic emerges as a promising beyond-CMOS computing paradigm, evaluating its robustness against fabrication imperfections and thermal noise becomes crucial. The Operational Domain framework provides a foundation for such assessments but overlooks key Figures of Merit (FoMs) such as temperature robustness, alternative input paradigms, and I/O integrity validation. This paper introduces new methodologies that extend operational domains to incorporate these factors, enabling a more comprehensive analysis of SiDB gate stability. Implemented in the open-source Operational Domain Explorer, these methods provide high-resolution robustness evaluations. Our results reveal that critical temperature domains exhibit highly uneven structures, previously thermally unstable gates can function at room temperature under specific material parameters, and enforcing I/O integrity significantly reduces temperature stability. By addressing these overlooked aspects, this work refines SiDB robustness evaluation and provides new insights into optimizing both simulation methodologies and fabrication strategies for more reliable SiDB-based computing architectures. Read more

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Ashenhurst-Curtis Decomposition Using Don’t Cares

Published in International Workshop on Logic & Synthesis (IWLS), 2025

Ashenhurst-Curtis decomposition (ACD) is a Boolean decomposition technique widely used in logic synthesis for tasks such as the decomposition of multi-valued relations, the encoding of multi-valued networks, and technology mapping into standard cells for ASICs and lookup tables (LUTs) for FPGAs. A recent truth-table-based implementation of ACD has proven effective for delay-driven LUT mapping while also reducing the number of lookup tables for improved area efficiency. This method offers better runtime performance and a higher decomposition success rate, making ACD a practical and scalable technique for modern synthesis flows. However, it does not leverage the additional flexibility provided by don’t-care conditions. In this paper, we enhance ACD by incorporating controllability don’t-cares extracted from cuts. By exploiting these additional degrees of freedom during decomposition, the proposed method achieves a higher decomposition success rate and a lower average number of LUTs per cut function. Specifically, we demonstrate that the decomposition success rate of practical functions into 6-LUTs increases from 51% to 53.4%, while the average number of LUTs per decomposition decreases from 2.50 to 2.46. Moreover, in cases where state-of-the-art methods struggle to find valid decompositions—particularly with large fixed free sets—our method shows clear improvements. Success rates increase from 16.11% to 23.27% for four late-arriving variables and from 1.58% to 4.44% for five, with only a 1.5× runtime overhead. Read more

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Live Demonstration: An Application for Layout Resilience Analysis of Silicon Dangling Bond Logic

Published in IEEE International Symposium on Circuits and Systems, 2025

This demonstration presents the Operational Domain Explorer, a PyQt6-based application designed for computationally efficient resilience analysis of Silicon Dangling Bond (SiDB) logic layouts. Leveraging novel algorithms, the tool significantly reduces the simulation load required for operational domain evaluations, supporting real-time, multi-dimensional visualizations and advancing SiDB layout reliability. Read more

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QuickTrace: An Efficient Contour Tracing Algorithm for Defect Robustness Simulation of Silicon Dangling Bond Logic

Published in IEEE International Symposium on Circuits and Systems, 2025

As traditional transistor scaling reaches its physical and economic limits, Silicon Dangling Bond (SiDB) logic is emerging as a promising post-CMOS technology for atomic-scale computation. However, despite mitigation efforts, atomic defects persist on the hydrogen-passivated silicon surface and remain challenging to eliminate. Since SiDB logic is highly sensitive to these charged atomic defects, efficient defect robustness simulation is essential for reliable SiDB logic design and successful operation. Existing simulation methods, however, are inefficient, limiting their practical applicability. To address this shortcoming, we present QuickTrace, an efficient algorithm to simulate the defect robustness of SiDB logic. QuickTrace uses contour tracing to identify the boundary in the simulation area between operational and non-operational states caused by defect positions, allowing defect robustness to be simulated with significantly fewer simulator calls. Experimental evaluations show that QuickTrace precisely and accurately computes defect robustness while avoiding the need to consider 88% of potential defect positions in simulations and thus reducing runtime by the same percentage-compared to the state-of-the-art approach. This enables efficient and scalable defect robustness simulation of SiDB logic for the first time, contributing to the advancement of SiDB technology as a promising post-CMOS technology. Read more

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Bias by Design: Diversity Quantification to Mitigate Structural Bias Effects in AIG Logic Optimization

Published in Design, Automation and Test in Europe, 2025

And-Inverter Graphs (AIGs) are a fundamental data structure in logic optimization, widely used in modern electronic design automation. A persistent challenge in AIG optimization is structural bias, where the initial graph structure strongly influences optimization quality by restricting the search space, often resulting in subpar outcomes. Existing methods address this issue by running multiple optimization workflows in parallel, relying on a trial-and-error approach that lacks a systematic way to measure structural diversity or assess effectiveness, making them computationally expensive and inefficient. This paper introduces a novel framework for systematically evaluating and reducing structural bias by measuring structural diversity, defined as the degree of dissimilarity between AIG graphs. Several traditional graph similarity measures and newly proposed AIG-specific metrics, including the Rewrite, Refactor, and Resub Scores, are explored. Results reveal limitations in traditional graph similarity metrics and highlight the effectiveness of the proposed AIG-specific measures in quantifying structural dissimilarity. Notably, the RRR Score shows a strong correlation (Pearson correlation coefficient, r = 0.79) with post-optimization structural differences, demonstrating the reliability of the metric in capturing meaningful variations between AIG structures. This work addresses the challenge of quantifying structural bias and offers a methodology that can potentially improve optimization outcomes, with future extensions applicable to other logic graph types. Read more

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Towards Fast Automatic Design of Silicon Dangling Bond Logic

Published in Design, Automation and Test in Europe, 2025

In recent years, Silicon Dangling Bond (SiDB) logic has emerged as a promising beyond-CMOS technology. Unlike conventional circuit technology, where logic is realized through transistors, SiDB logic utilizes quantum dots with variable charge states. By strategically arranging these dots, logic functions can be constructed. However, determining such arrangements is a tremendously complex task. Because of that, the automatic obtainment of SiDB logic implementations is inefficient. To address this challenge, we propose an idea to speed up the design process by utilizing dedicated search space pruning strategies. Initial results show that the combined pruning techniques yield 1) a drastic reduction of the search space, and 2) a corresponding reduction in runtime by up to a factor of 33. Read more

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Late Breaking Results: Physical Co-Design for Field-coupled Nanocomputing

Published in Design, Automation and Test in Europe, 2025

Field-coupled Nanocomputing (FCN), a class of post-CMOS technologies operating at the nanoscale without the flow of electricity, is becoming a reality due to advancements in simulating and manufacturing logic gates using Silicon Dangling Bonds (SiDBs). Efficient physical design methodologies are crucial for the performance, area efficiency, reliability, and manufacturability of FCN circuits. However, despite considerable progress in developing algorithms and tools tailored to FCN physical design, achieving efficient results still requires a co-design approach, necessitating expert manual refinement similar to the CMOS design process. To this end, we introduce a GUI-based tool that combines both automation and expert adjustments, enabling designers to easily optimize and modify FCN layouts. To demonstrate its potential, a designer used the tool to reduce the area of the best-known layout for the benchmark circuit cm82a by over 15% in less than a minute. Additionally, the tool is publicly available as open-source at https://github.com/cda-tum/mnt-designer. Read more

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Efficient and Scalable Post-Layout Optimization for Field-coupled Nanotechnologies

Published in IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, 2025

As conventional computing technologies approach their physical limits, the quest for increased computational power intensifies, heightening interest in post-CMOS technologies. Among these, Field-coupled Nanocomputing (FCN), which operates through the repulsion of physical fields at the nanoscale, emerges as a promising alternative. However, realizing specific functionalities within this technology necessitates the development of dedicated FCN physical design methods. Although various methods have been proposed, their reliance on heuristic approaches often results in suboptimal quality, highlighting a significant opportunity for enhancement. In the realm of conventional CMOS design, post-layout optimization techniques are employed to capitalize on this potential, yet such methods for FCN are either not scalable or lack efficiency. This work bridges this gap by introducing the first scalable and efficient post-layout optimization algorithm for FCN. Experimental evaluations demonstrate the efficiency of this approach: when applied to layouts obtained by a state-of-the-art heuristic method, the proposed post-layout optimization achieves area reductions of up to 73.75% (45.58% on average). This significant improvement underscores the transformative potential of post-layout optimization in FCN. Moreover, unlike existing algorithms, the method exhibits scalability even in optimizing layouts with over 20 million tiles. Implementations of the proposed methods are publicly available as part of the Munich Nanotech Toolkit (MNT) at https://github.com/cda-tum/fiction. Read more

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Physical Design for Field-coupled Nanocomputing with Discretionary Cost Objectives

Published in IEEE Latin American Symposium on Circuits and Systems, 2025

This work was a Best Paper Award Candidate at LASCAS 2025. Read more

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On-the-fly Defect-Aware Design of Circuits based on Silicon Dangling Bond Logic

Published in IEEE International Conference on Nanotechnology, 2024

Silicon Dangling Bonds (SiDBs) have emerged as a promising post-CMOS technology for achieving ultra-low power dissipation, establishing themselves as a highly anticipated and environmentally friendly competitor in the realm beyond conventional CMOS. To support the SiDB logic framework, design automation approaches have rapidly evolved. However, at the atomic scale of SiDBs, material imperfections pose a significant roadblock in scaling these devices. Consequently, established design automation flows, which are defect-agnostic, are inadequate and have not kept pace with the latest experimental findings and advances in fabrication capabilities. A first attempt was recently proposed that extends established defect-agnostic physical design methods by rudimentary defect-aware capabilities. While promising at first glance, in this work, we show that this first attempt yields unsatisfactory results. Subsequently, we present a novel approach that automatically designs a tailored SiDB gate on-the-fly whenever an SiDB gate encounters atomic defects in its vicinity, thereby incorporating these atomic defects into its layout as an integral part. Our experimental evaluations confirm that the proposed approach is capable of designing SiDB circuits of significant complexity and size, even in the presence of atomic defects for the first time. Therefore, this work contributes to advancing this promising post-CMOS technology. Read more

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Unifying Figures of Merit: A Versatile Cost Function for Silicon Dangling Bond Logic

Published in IEEE International Conference on Nanotechnology, 2024

As Silicon Dangling Bond (SiDB) logic emerges as a promising beyond-CMOS technology, Figures of Merit (FoMs) to assess gate performance become crucial in implementing devices that are robust against environmental variations. Constructing robust SiDB logic involves designing gates that excel across multiple FoMs. However, there exist no clear guidelines on the ideal ranges for FoM values, nor a systematic approach to designing SiDB gates that optimize across multiple FoMs. Motivated by this, this work focuses on addressing the following key objectives: 1) Introduction of a new FoM, called Band Bending Resilience. 2) Determination, presentation, and detailed discussion on the best achievable values for each FoM for all 2-input Boolean functions. 3) Presentation of the versatile cost function x, unifying multiple FoMs tailored to specific application requirements and priorities. 4) Implementation of the optimization strategy using the cost function x, which aims at designing SiDB logic with minimal cost, ensuring an optimal balance between all FoMs. Overall, this research contributes significantly to the understanding of SiDB logic, establishing a basis for future progress in the field. Read more

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Unlocking Flexible Silicon Dangling Bond Logic Designs on Alternative Silicon Orientations

Published in IEEE International Conference on Nanotechnology, 2024

With the impending plateau of Moore’s Law, the search for novel computational paradigms has intensified. Silicon dangling bond (SiDB) logic emerges as a promising avenue in this quest, leveraging the quantum-dot-like properties of SiDBs and atomically precise fabrication techniques to realize logic functions at the nanometer scale. Advances in computer-aided design (CAD) tools specialized for SiDB logic exploration have also opened the door to novel logic research from the gate- to application-level. This paper introduces a lattice vector formulation for SiDB logic designs on alternative silicon lattice orientations, enabling the exploration of logic gates on arbitrary lattice orientations and addressing the limitations of previous SiDB logic research confined to the H-Si(100)-2x1 surface. A comprehensive workflow for designing standard tile libraries compatible with design automation frameworks is proposed, facilitating the scaling of SiDB layouts to large-scale systems implementation on multiple lattice orientations. We demonstrate the proposed lattice vector representation and the library design workflow through a case study on the H-Si(111)-1x1 surface, showcasing the first logic gates designed for this orientation. This advancement opens new avenues for SiDB logic research, enabling rigorous evaluations of various lattice orientations for future logic design studies and experimental investigations. Read more

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A* is Born: Efficient and Scalable Physical Design for Field-coupled Nanocomputing

Published in IEEE International Conference on Nanotechnology, 2024

Field-coupled Nanocomputing (FCN) has emerged as a promising alternative to traditional CMOS technology, driven by recent advancements in atomic-scale logic gate fabrication and simulation. However, the efficient placement and routing of logic functions remain significant challenges, with existing algorithms lacking scalability or quality. In this paper, we present a novel method aimed at addressing these challenges by focusing on the generation of layouts with outstanding quality in a fraction of the time compared to existing approaches. Through extensive experimentation, we demonstrate that our method significantly reduces area overhead, outperforming two state-of-the-art heuristics by more than 70% and 24%, respectively, while achieving these results at a remarkable 460 times faster pace compared to the latter. Furthermore, we contribute to open science by releasing our algorithm as an open-source implementation, fostering collaboration and further advancements in the field of FCN. Read more

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Reducing Wire Crossings in Field-Coupled Nanotechnologies

Published in IEEE International Conference on Nanotechnology, 2024

In the realm of circuit design, emerging technologies such as Field-Coupled Nanotechnologies (FCN) provide unique opportunities compared to conventional transistor-based logic. However, FCN also introduces a critical concern: the substantial impact of wire crossings on circuit robustness. These crossings are either unrealizable or can severely degrade signal integrity, posing significant obstacles to efficient circuit design. To address this challenge, we propose a novel approach focused on reducing wire crossings in FCN circuits. Our methodology introduces a combination of LUT mapping and decomposition aimed at producing advantageous network structures during logic synthesis to minimize wire crossings. This new optimization metric is prioritized over node count and critical path length to effectively tackle this challenge. Through empirical evaluations, we demonstrate the effectiveness of the proposed approach in reducing a first approximation for wire crossings by 41.69%. This research significantly contributes to advancing wire crossing optimization strategies in emerging circuit technologies, paving the way for more reliable and efficient designs in the post-CMOS logic era. Read more

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Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions

Published in IEEE International Conference on Nanotechnology, 2024

This work won the Best Presentation Award at IEEE NANO 2024. Read more

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Ending the Tyranny of the Clock: SAT-based Clock Number Assignment for Field-coupled Nanotechnologies

Published in IEEE International Conference on Nanotechnology, 2024

This paper presents an algorithm for clock number assignment in the physical design process of Field-coupled Nanocomputing (FCN), a set of promising beyond-CMOS technologies that manipulate physical fields instead of electrical currents for computation and information transmission. Clocking has traditionally been a significant obstacle to the scalability of FCN physical design algorithms, requiring pre-defined clocking schemes that limit the quality of circuit layouts and add complexity to the design process. Our proposed method utilizes Boolean Satisfiability (SAT) solving to facilitate the assignment of clock numbers without the need for predefined clocking, while ensuring compliance with technological constraints on information flow and synchronization. Via an experimental evaluation, we confirm the proposed algorithm’s versatility to reconstruct clock assignments for diverse clocking schemes in reasonable runtime, and its scalability up to layouts with a half-million tiles. Thereby, we are potentially paving the way for a new era of physical design algorithms that are not constrained by the limitations of predefined clocking schemes. This research suggests a move towards physical design strategies adapted from conventional design automation, potentially mitigating one of the major challenges to FCN’s further development. Read more

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The Munich Nanotech Toolkit (MNT)

Published in IEEE International Conference on Nanotechnology, 2024

As traditional computing technologies near their physical limits, the demand for beyond-CMOS alternatives intensifies. Among these, Field-coupled Nanocomputing (FCN) emerges as a class of multiple promising candidates, offering computational capabilities at a sub-nanometer scale. Breakthroughs in the fabrication of Silicon Dangling Bonds (SiDBs) exemplified by sub-30 nm² OR gates and wire segments underscore FCN’s potential to revolutionize computing paradigms. However, existing software tools for FCN circuit design lack functionality and suffer from maintenance issues. Addressing this gap, in this work, we introduce the open-source Munich Nanotech Toolkit (MNT), providing accessible interfaces including a Command-Line Interface, a C++ header-only library, and Python bindings. Our toolkit adheres to modern software standards, ensuring continuous integration and testing across diverse platforms with substantial code coverage. This toolkit aids in advancing FCN design automation, and serves as a sandbox for designers and researchers in the domain, paving the way towards the beyond-CMOS era. Read more

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Late Breaking Results: Wiring Reduction for Field-coupled Nanotechnologies

Published in Design Automation Conference, 2024

The emergence of Field-coupled Nanocomputing (FCN) as a green and atomically-sized post-CMOS technology introduces a unique challenge for the development of physical design methods: unlike conventional computing, wire segments in FCN entail the same area and delay costs as standard gates. Hence, it is imperative to reconsider physical design strategies tailored for FCN to effectively address this distinctive characteristic. This paper unveils a recent breakthrough in minimizing the number of wire segments by an average of 20.13%, which, due to the high cost associated with wires, also leads to an average decrease of 34.10% in overall area and 19.84% in critical path length. Furthermore, unlike existing post-layout optimization algorithms, the proposed method maintains scalability even for layouts encompassing millions of tiles. Read more

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Thinking Outside the Clock: Physical Design for Field-coupled Nanocomputing with Deep Reinforcement Learning

Published in International Symposium on Quality Electronic Design, 2024

Recent advances in atom-scale manufacturing are paving the way toward the emergence of Field-coupled Nanocomputing (FCN) as a viable real-world post-CMOS technology. Current FCN-specific solutions for placement and routing of logic functions are at risk of falling behind manufacturing capabilities. The problem lies in the fact that existing algorithms are either optimal in their result quality but do not scale; or are scalable, but produce results of sub-par quality limited to select clocking schemes. Furthermore, most existing approaches are tailored toward a concrete FCN implementation, limiting their applicability across the domain. To address these challenges, we propose a novel approach that utilizes deep reinforcement learning to learn the placement of logic elements and incorporate established routing strategies directly into the placement step. By relying only on abstract signal flow directions, this solution is technology-agnostic and therefore applicable to any FCN implementation, layout topology, or clocking scheme. The proposed approach is experimentally evaluated on a set of established benchmark functions common in the domain. While a stateof-the-art exact approach is limited to designing layouts for functions containing a maximum of around 40 gates, the proposed approach is able to generate solutions for all functions included in the considered benchmark sets, while reducing the layout area by an average of 59 % compared to the state-of-the-art heuristic. Furthermore, the proposed algorithm is made available to the scientific community as an open-source implementation. Read more

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Towards Atomic Defect-Aware Physical Design of Silicon Dangling Bond Logic on the H-Si(100)-2×1 Surface

Published in Design, Automation and Test in Europe Conference, 2024

Recent advancements in Silicon Dangling Bond (SiDB) fabrication have transitioned from manual to automated processes. However, sub-nanometer substrate defects remain a significant challenge, thus preventing the fabrication of functional logic. Current design automation techniques lack defect-aware strategies. This paper introduces an idea for a surface defect model based on experimentally verified defects, which can be applied to enhance the robustness of established gate libraries. Additionally, a prototypical automatic placement and routing algorithm is presented, utilizing STM data from physical experiments to obtain dot-accurate circuitry resilient to atomic surface defects. Initial evaluations on surfaces with varying defect rates demonstrate their critical impact, suggesting that fabrication processes must achieve defect rates of around 0.1 % to further advance this circuit technology. Read more

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MNT Bench: Benchmarking Software and Layout Libraries for Field-coupled Nanocomputing

Published in Design, Automation and Test in Europe Conference, 2024

As Field-coupled Nanocomputing (FCN) gains traction as a viable post-CMOS technology, the EDA community lacks public benchmarks to evaluate the performance of academic and commercial design tools. We propose MNT Bench to address this gap by providing a platform for researchers to compare algorithms across a diverse set of benchmarks generated by multiple physical design tools. These benchmarks span various clocking schemes and gate libraries, with MNT Bench being consistently updated to integrate the latest advancements in the field. In fact, using MNT Bench, we were able to provide layouts that are substantially better (in terms of area) than everything the community generated thus far. Read more

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Simulating Charged Defects in Silicon Dangling Bond Logic Systems to Evaluate Logic Robustness

Published in IEEE Transactions on Nanotechnology, 2024

Recent research interest in emerging logic systems based on quantum dots has been sparked by the experimental demonstration of nanometer-scale logic devices composed of atomically sized quantum dots made of silicon dangling bonds (SiDBs), along with the availability of SiQAD, a computer-aided design tool designed for this technology. Latest design automation frameworks have enabled the synthesis of SiDB circuits that reach the size of 32 x 103 nm²—orders of magnitude more complex than their hand-designed counterparts. However, current SiDB simulation engines do not take defects into account, which is important to consider for these sizable systems. This work proposes a formulation for incorporating fixed-charge simulation into established ground state models to cover an important class of defects that has a non-negligible effect on nearby SiDBs at the 10 nm scale and beyond. The formulation is validated by implementing it into SiQAD’s simulation engine and computationally reproducing experiments on multiple defect types, revealing a high level of accuracy. The new capability is applied towards studying the tolerance of several established logic gates against the introduction of a single nearby defect to establish the corresponding minimum required clearance. These findings are compared against existing metrics to form a foundation for logic robustness studies. Read more

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The Need for Speed: Efficient Exact Simulation of Silicon Dangling Bond Logic

Published in Asia and South-Pacific Design Automation Conference, 2024

The Silicon Dangling Bond (SiDB) logic platform, an emerging computational beyond-CMOS nanotechnology, is a promising competitor due to its ability to achieve integration density and clock speed values that are several orders of magnitude higher compared to current CMOS fabrication nodes. However, the exact physical simulation of SiDB layouts, which is an essential component of any design validation workflow, is computationally expensive. In this paper, we propose a novel algorithm called QuickExact, which aims to be both, efficient and exact. To this end, we are introducing three techniques, namely 1) Physically-informed Search Space Pruning, 2) Partial Solution Caching, and 3) Effective State Enumeration. Extensive experimental evaluations confirm that, compared to the state-of-the-art algorithm, the resulting approach leads to a paramount runtime advantage of more than a factor of 5000 on randomly generated layouts and more than a factor of 2000 on an established gate library. Read more

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Post-Layout Optimization for Field-coupled Nanotechnologies

Published in International Symposium on Nanoscale Architectures, 2023

While conventional computing technologies reach their limits, the demand for computation power keeps growing, fueling the interest in post-CMOS technologies. One promising contestant in this domain is Field-coupled Nanocomputing (FCN), which conducts computations based on the repulsion of physical fields at the nanoscale. However, to realize a dedicated functionality in this technology design methods are needed that create corresponding FCN layouts. While several methods for FCN layout generation have been proposed in the past, the underlying complexity requires them to resort to heuristic approaches—leading to results of sub-par quality and offering room for improvement. In conventional CMOS design, post-layout optimization methods are available to exploit this potential for further improvement. Unfortunately, no such methods exists yet for FCN. In this work, we are addressing this gap and introduce the first post-layout optimization approach for FCN. Experimental evaluations show the benefits of the approach: Applied to layouts generated by two complementary state-of-the-art methods, the proposed post-layout optimization allows for a further area reduction of 50.79 % and 20.00 % on average, respectively—confirming the potential of post-layout optimization for FCN. Read more

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Reducing the Complexity of Operational Domain Computation in Silicon Dangling Bond Logic

Published in International Symposium on Nanoscale Architectures, 2023

Silicon Dangling Bonds (SiDBs) constitute a beyond-CMOS computational nanotechnology platform that enables higher integration density and lower power consumption than contemporary CMOS nodes. Recent manufacturing breakthroughs in the domain sparked the interest of academia and industry alike in the race for a green computation future at the nanoscale. However, as the fabrication of SiDBs requires atomic precision, SiDB logic systems are inherently susceptible to environmental defects and material variations, which inevitably occur. The Operational Domain is a methodology to evaluate the resilience of SiDB logic against physical parameter variations. However, state-of-the-art implementations require a quadratic number of exponentially complex physical simulator calls to assess the operational domain. This paper presents two novel algorithms to obtain operational domains in an efficient fashion: one based on flood fill, and one based on contour tracing. Experimental evaluations confirm that they reduce the number of required simulator calls by 70.87 % and 95.29 %, respectively. Particularly contour tracing achieves the shift from a quadratic to a linear relation, thereby reducing the complexity and paving the way for realizing reliable SiDB-based computing systems. Read more

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Minimal Design of SiDB Gates: An Optimal Basis for Circuits Based on Silicon Dangling Bonds

Published in International Symposium on Nanoscale Architectures, 2023

Silicon Dangling Bonds (SiDBs) present a promising computational technology that goes beyond traditional CMOS. It enables the creation of circuitry using single atoms as elementary components. Since contemporary computational technologies approach their physical limits, SiDBs have attracted significant interest from both academia and industry. SiDBs allow for gate implementation of Boolean functions to realize arbitrary circuit logic. Hence, improvements at the gate level propagate through to the circuit level. Although fabrication capabilities are advancing rapidly and initial design automation methodologies have been proposed, the current design of SiDB gates is primarily based on manual labor. This paper presents an approach capable of designing SiDB gates using the minimum number of SiDBs possible for a given Boolean function, thus minimizing gate cost and providing an optimal basis for SiDB circuits. This methodology simplifies SiDB circuit designs and their corresponding manufacturing processes significantly, thereby accelerating the progress of this promising nanotechnology. Read more

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Late Breaking Results From Hybrid Design Automation for Field-coupled Nanotechnologies

Published in Design Automation Conference, 2023

Recent breakthroughs in atomically precise manufacturing are paving the way for Field-coupled Nanocomputing (FCN) to become a real-world post-CMOS technology. This drives the need for efficient and scalable physical design automation methods. However, due to the problem’s NP-completeness, existing solutions either generate designs of high quality, but are not scalable, or generate designs in negligible time but of poor quality. In an attempt to balance scalability and quality, we created and evaluated a hybrid approach that combines the best of established design methods and deep reinforcement learning. This paper summarizes the obtained results. Read more

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Design Automation for Cryogenic CMOS Circuits

Published in Design Automation Conference, 2023

Cryogenic CMOS circuits operate at temperatures close to absolute zero and are essential in many applications such as controllers for quantum computing but also medical engineering, space technology, or physical instruments. However, operating circuits at cryogenic temperatures fundamentally changes the underlying semiconductor physics that governs the CMOS transistor—rendering existing design automation approaches infeasible. In this work, we propose and implement the first end-to-end approach that enables design automation for cryogenic CMOS circuits. To this end, we (1) perform the first-of-its-kind measurements of commercial 5 nm FinFET transistors from 300 K down to 10 K, (2) use the results to validate and calibrate the first cryogenic-aware industrial-standard compact model for FinFET technology, (3) create cryogenic-aware standard cell libraries that are compatible with the existing EDA tool flows, and (4) propose an initial cryogenic-aware logic synthesis approach that re-uses established design automation expertise but optimizes it for cryogenic purposes. Evaluations, comparisons, and discussions of all these novel contributions confirm the applicability and validity of the resulting cryogenic-aware design automation flow. Read more

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Scalable Physical Design for Silicon Dangling Bond Logic: How a 45° Turn Prevents the Reinvention of the Wheel

Published in IEEE International Conference on Nanotechnology, 2023

With the ever-increasing demands of computing, post-CMOS technologies are sought after. Field-coupled Nanocomputing (FCN), which relies on physical field repulsion, is a class of technologies for energy-efficient computing. While the physical design for Quantum-dot Cellular Automata (QCA) has been researched for more than 20 years, the methodologies for its promising successor, namely Silicon Dangling Bonds (SiDBs), have yet to catch up. To prevent reinventing the wheel and utilizing the 20 years of development in QCA, this paper presents a methodology to create SiDB designs based on existing QCA design approaches by a 45° rotation, implemented as a remapping algorithm. The presented approach enables the direct translation of QCA layouts to SiDB ones with minimal overhead and allows to tap knowledge from decades of research. Read more

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Temperature Behavior of Silicon Dangling Bond Logic

Published in IEEE International Conference on Nanotechnology, 2023

Silicon Dangling Bonds (SiDBs) on the hydrogen-passivated silicon surface have emerged as a promising competitor in the realm of beyond-CMOS computational technologies. They have attracted the attention of academia and industry due to their greatly increased integration density and energy efficiency compared to contemporary fabrication nodes. Since information propagation and computation in the SiDB domain are based on electrostatic field coupling, SiDBs are considered as a room temperature-enabled technology. However, the effect of temperature on SiDB-based gates and their operation has not yet been considered. Consequently, established design automation flows and gate library proposals are temperature-agnostic without any guarantee of their operability in real-world scenarios. In this paper, we investigate for the first time the effect of temperature on the operation of SiDB-based gates. To this end, we utilize a newly developed temperature-aware simulator and exhaustively evaluate previously fabricated gates and theoretically proposed standard libraries. The results reveal significant temperature-sensitivity of many gates, highlighting the crucial role of considering temperature behavior in the realization of SiDB-based gates. Therefore, it is imperative to minimize the use of such temperature-sensitive components in future designs and to develop more robust standard gates. This research serves as the foundation for subsequent studies and is vital for the acceleration of the development of this promising green nanotechnology. Read more

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QuickSim: Efficient and Accurate Physical Simulation of Silicon Dangling Bond Logic

Published in IEEE International Conference on Nanotechnology, 2023

Silicon Dangling Bonds have established themselves as a promising competitor in the field of beyond-CMOS technologies. Their integration density and potential for energy dissipation advantages of several orders of magnitude over conventional circuit technologies sparked the interest of academia and industry alike. While fabrication capabilities advance rapidly and first design automation methodologies have been proposed, physical simulation effectiveness has yet to keep pace. Established algorithms in this domain suffer either from exponential runtime behavior or subpar accuracy levels. In this work, we propose a novel algorithm for the physical simulation of Silicon Dangling Bond systems based on statistical methods that offers both a time-to-solution and an accuracy advantage over the state of the art by more than one order of magnitude and a factor of more than three, respectively, as demonstrated by an exhaustive experimental evaluation. Read more

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Exploiting the Third Dimension: Stackable Quantum-dot Cellular Automata

Published in International Symposium on Nanoscale Architectures, 2022

The exponential growth of transistor density in integrated circuits is doomed to fail at the limits of physics in the foreseeable future. Quantum-dot Cellular Automata (QCA) is a post-CMOS contestant from the emerging Field-coupled Nanocomputing (FCN) paradigm which offers computations with tremendously low power dissipation. Recent physical accomplishments in this area also motivated the developments of corresponding design automation methods. However, although the higher integration density of QCA makes this technology a promising candidate for stacked, i.e. cuboid-like, chip architectures, all design automation solutions proposed thus far are limited to 2-dimensional architectures only. This work showcases the potential when the third dimension is additionally utilized. To this end, we must overcome certain obstacles for which corresponding solutions are proposed. Case studies on important regular structures such as bitwise AND/OR, binary adders, or multiplexers—for which we provide automatic generation scripts—confirm that exploiting the third dimension in this fashion yields a prodigious reduction in area occupation and cell count, differing by several orders of magnitude compared to the state of the art. Read more

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Efficient Multi-Path Signal Routing for Field-coupled Nanotechnologies

Published in International Symposium on Nanoscale Architectures, 2022

Establishing itself among the vanguard of beyond-CMOS candidates, Field-coupled Nanocomputing (FCN) has advanced in recent times due to fabrication breakthroughs of Silicon Dangling Bonds (SiDBs). At the foundation of these breakthroughs, experimental demonstrations showcase the feasibility of FCN logic components and wire segment implementations at the physical limits of scaling. However, automatic design methods for this highly-promising technology remain scarce, as they are impeded by the necessity to conform to particular constraints that differ from those in CMOS technologies. Previously proposed approaches are restricted by their inability to overcome scalability limitations and/or their failure to generate results of adequate quality. In this work, we aim to improve this state of the art %overcome the preceding techniques by addressing the epicenter of performance inadequacy and proposing a distinctive multi-path FCN routing algorithm that is explicitly adjusted to the design constraints dictated by FCN technologies. The resulting approach can be parameterized to generate signal routings for almost arbitrary FCN placements or, in case this is impossible, pinpoint the designer to the unsatisfied connections. Experimental evaluations confirm these abilities on an established benchmark set and demonstrate a runtime advantage of several orders of magnitude over a state-of-the-art physical design algorithm. Read more

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Hexagons are the Bestagons: Design Automation for Silicon Dangling Bond Logic

Published in Design Automation Conference, 2022

Field-coupled Nanocomputing (FCN) defines a class of post-CMOS nanotechnologies that promises compact layouts, low power operation, and high clock rates. Recent breakthroughs in the fabrication of Silicon Dangling Bonds (SiDBs) acting as quantum dots enabled the demonstration of a sub-30 nm2 OR gate and wire segments. This motivated the research community to invest manual labor in the design of additional gates and whole circuits which, however, is currently severely limited by scalability issues. In this work, these limitations are overcome by the introduction of a design automation framework that establishes a flexible topology based on hexagons as well as a corresponding Bestagon gate library for this technology and, additionally, provides automatic methods for physical design. By this, the first design automation solution for the promising SiDB platform is proposed. In an effort to support open research and open data, the resulting framework as well as all design and code files are made publicly available. Read more

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Three-Input NPN Class Gate Library for Atomic Silicon Quantum Dots

Published in Design & Test, 2022

This article proposes a complete 3-input gate library using atomic silicon quantum-dots made of silicon dangling bonds (SiDBs). This emerging technology aims to achieve ultra-low energy dissipation and high-density integration using field interactions rather than the flow of electric current. Our main contribution is a SiDB gate library of ten logic gates to cover all 256 3-input Boolean functions by utilizing NPN equivalence classes. Finally, the results present detailed properties of our designs and discuss their robustness against environmental variations. We use SiQAD, a state-of-art CAD tool specialized for SiDB technologies, for simulation and verification. Read more

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One-pass Synthesis for Field-coupled Nanocomputing Technologies

Published in Asia and South Pacific Design Automation Conference, 2021

This work was a Best Paper Award candidate at ASP-DAC 2021. Read more

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Clustering-Guided SMT(LRA) Learning

Published in International Conference on integrated Formal Methods, 2020

In the SMT(LRA) learning problem, the goal is to learn SMT(LRA) constraints from real-world data. To improve the scalability of SMT(LRA) learning, we present a novel approach called SHREC which uses hierarchical clustering to guide the search, thus reducing runtime. A designer can choose between higher quality (SHREC1) and lower runtime (SHREC2) according to their needs. Our experiments show a significant scalability improvement and only a negligible loss of accuracy compared to the current state-of-the-art. Read more

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Verifying Safety Properties of Robotic Plans operating in Real-World Environments via Logic-based Environment Modeling

Published in International Symposium On Leveraging Applications of Formal Methods, Verification and Validation, 2020

These days, robotic agents are finding their way into the personal environment of many people. With robotic vacuum cleaners commercially available already, comprehensive cognition-enabled agents assisting around the house autonomously are a highly relevant research topic. To execute these kinds of tasks in constantly changing environments, complex goal-driven control programs, so-called plans, are required. They incorporate perception, manipulation, and navigation capabilities among others. As with all technological innovation, consequently, safety and correctness concerns arise. Read more

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ToPoliNano and fiction: Design Tools for Field-coupled Nanocomputing (Invited Paper)

Published in Euromicro Conference on Digital System Design, 2020

Field-coupled Nanocomputing (FCN) is a computing concept with several promising post-CMOS candidate implementations that offer tremendously low power dissipation and highest processing performance at the same time. Two of the manifold physical implementations are Quantum-dot Cellular Automata (QCA) and Nanomagnet Logic (NML). Both inherently come with domain-specific properties and design constraints that render established conventional design algorithms inapplicable. Accordingly, dedicated design tools for those technologies are required. This paper provides an overview of two leading examples of such tools, namely fiction and ToPoliNano. Both tools provide effective methods that cover aspects such as placement, routing, clocking, design rule checking, verification, and logical as well as physical simulation. By this, both freely available tools provide platforms for future research in the FCN domain. Read more

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Verification for Field-coupled Nanocomputing Circuits

Published in Design Automation Conference, 2020

With the decline of Moore’s Law, several post-CMOS technologies are currently under heavy consideration. Promising candidates can be found in the class of Field-coupled Nanocomputing (FCN) devices as they allow for highest processing performance with tremendously low energy dissipation. With upcoming design automation in this domain, the need for formal verification approaches arises. Unfortunately, FCN circuits come with certain domain-specific properties that render conventional methods for the verification non-applicable. In this paper, we investigate this issue and propose a verification approach for FCN circuits that addresses this problem. For the first time, this provides researchers and engineers with an automatic method that allows them to check whether an obtained FCN circuit design indeed implements the given/desired function. A prototype implementation demonstrates the applicability of the proposed approach. Read more

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Design Automation for Field-coupled Nanotechnologies

Published in IEEE Computer Society Annual Symposium on VLSI, 2020

This work won the Best Student Forum Paper Award at ISVLSI 2020. Read more

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Bail on Balancing: An Alternative Approach to the Physical Design of Field-coupled Nanocomputing Circuits

Published in IEEE Computer Society Annual Symposium on VLSI, 2020

This work was a Best Paper Award candidate at ISVLSI 2020. Read more

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On the Impact of the Synchronization Constraint and Interconnections in Quantum-dot Cellular Automata

Published in Microprocessors and Microsystems: Embedded Hardware Design, 2020

Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology with remarkable performance and energy efficiency. Computation and information transfer in QCA are based on field forces rather than electric currents. As a consequence, new strategies are required for design automation approaches in order to cope with the arising challenges. One of these challenges is the transport of information, which is affected by two particularities of the QCA technology. First, information flow in QCA is controlled by external clocks, and second, QCA is a planar technology in which gates, as well as interconnections, are mostly located in the same layer. The former demands proper synchronization already during the circuit design phase, while the latter results in high area costs for interconnections. This work focuses on both constraints and discusses its impact on the implementation of QCA circuits. Further, the concept of local and global synchronicity in QCA circuits is explored. The obtained results indicate that relaxing the global synchronicity constraint can reduce design size by about 70% while the throughput performance declines by similar values. Additionally, it can be shown that the impact of interconnections in QCA, like wires, fan-outs, and crossovers, is indeed substantial. That means, up to 75% of the total area is occupied by interconnections. Read more

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Towards Formal Verification of Plans for Cognition-enabled Autonomous Robotic Agents

Published in Euromicro Conference on Digital System Design, 2019

In this paper, we propose the first approach for verifying plans of cognition-enabled autonomous robots that perform everyday manipulation activities in human environments. Our methodology is based on the new Intermediate Plan Verification Language (IPVL) which is used to represent plans, environments, and robot belief states in one joint formal model. We devise a symbolic execution engine for IPVL and show the effectiveness of our overall verification methodology in a case study. Read more

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Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled Nanotechnologies

Published in IEEE Computer Society Annual Symposium on VLSI, 2019

Field-Coupled Nanocomputing (FCN) allows for conducting computations with a power consumption that is magnitudes below current CMOS technologies. Recent physical implementations confirmed these prospects and put pressure on the Electronic Design Automation (EDA) community to develop physical design methods comparable to those available for conventional circuits. While the major design task boils down to a place and route problem, certain characteristics of FCN circuits introduce further challenges in terms of dedicated clock arrangements which lead to rather cumbersome clocking constraints. Thus far, those constraints have been addressed in a rather unsatisfactory fashion only. Read more

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fiction: An Open Source Framework for the Design of Field-coupled Nanocomputing Circuits

Published in International Workshop on Logic & Synthesis, 2019

As a class of emerging post-CMOS technologies, Field-coupled Nanocomputing (FCN) devices promise computation with tremendously low energy dissipation. Even though ground breaking advances in several physical implementations like Quantum-dot Cellular Automata (QCA) or Nanomagnet Logic (NML) have been made in the last couple of years, design automation for FCN is still in its infancy and often still relies on manual labor. In this paper, we present an open source framework called fiction for physical design and technology mapping of FCN circuits. Its efficient data structures, state-of-the-art algorithms, and extensibility provide a basis for future research in the community. Read more

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Placement & Routing for Tile-based Field-coupled Nanocomputing Circuits is NP-complete

Published in ACM Journal on Emerging Technologies in Computing Systems, 2019

Field-coupled Nanocomputing (FCN) technologies provide an alternative to conventional CMOS-based computation technologies and are characterized by intriguingly low energy dissipation. Accordingly, their design received significant attention in the recent past. FCN circuit implementations like Quantum-dot Cellular Automata (QCA) or Nanomagnet Logic (NML) have already been built in labs and basic operations such as inverters, Majority, AND, OR, etc. are already available. The design problem basically boils down to the question how to place basic operations and route their connections so that the desired function results while, at the same time, further constraints (related to timing, clocking, path lengths, etc.) are satisfied. While several solutions for this problem have been proposed, interestingly no clear understanding about the complexity of the underlying task exists thus far. In this research note, we consider this problem and eventually prove that placement and routing for tile-based FCN circuits is NP-complete. By this, we provide a theoretical foundation for the further development of corresponding design methods. Read more

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Scalable Design for Field-coupled Nanocomputing Circuits

Published in Asia and South Pacific Design Automation Conference, 2019

Field-coupled Nanocomputing (FCN) technologies are considered as a solution to overcome physical boundaries of conventional CMOS approaches. But despite ground breaking advances regarding their physical implementation as e. g. Quantumdot Cellular Automata (QCA), Nanomagnet Logic (NML), and many more, there is an unsettling lack of methods for large-scale design automation of FCN circuits. In fact, design automation for this class of technologies still is in its infancy – heavily relying either on manual labor or automatic methods which are applicable for rather small functionality only. This work presents a design method which – for the first time – allows for the scalable design of FCN circuits that satisfy dedicated constraints of these technologies. The proposed scheme is capable of handling around 40000 gates within seconds while the current state-of-the-art takes hours to handle around 20 gates. This is confirmed by experimental results on the layout level for various established benchmarks libraries. Read more

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Evaluating the Impact of Interconnections in Quantum-Dot Cellular Automata

Published in Euromicro Conference on Digital System Design, 2018

Quantum-Dot Cellular Automata (QCA) are an emerging nanotechnology with remarkable performance and energy efficiency. Computation and information transfer in QCA is based on field forces rather than electric currents. As a consequence, new strategies are required for design automation approaches in order to cope with the arising challenges. One of these challenges rises from the fact that QCA is a planar technology. That means, logic gates as well as interconnection elements are mostly located in the same layer. Hence, it is expected that interconnections have higher influence on the final design costs than in conventional integrated technologies. For the first time, this paper presents an extensive study on the quantification of this impact. Therefore, we consider the entire design flow for QCA circuits from the initial synthesis (using different synthesis approaches) to the corresponding placement on a QCA grid. Then, we characterize the respectively obtained QCA circuits in terms of area, delay and energy costs. The obtained results indicate that the impact of interconnections in QCA is indeed substantial. Design costs including or not including interconnections differ by several orders of magnitudes, which motivates to completely re-think how logic synthesis for QCA circuits shall be conducted in the future. Read more

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Synchronization of Clocked Field-Coupled Circuits

Published in IEEE International Conference on Nanotechnology, 2018

Proper synchronization in clocked Field-Coupled Nanocomputing (FCN) circuits is a fundamental problem. In this work, we show for the first time that global synchronicity is not a mandatory requirement in clocked FCN designs and discuss the considerable restrictions that global synchronicity presents for sequential and large-scale designs. Furthermore, we propose a solution that circumvents design restrictions due to synchronization requirements and present a novel RS-latch. Read more

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An Exact Method for Design Exploration of Quantum-dot Cellular Automata

Published in Design, Automation and Test in Europe, 2018

Quantum-dot Cellular Automata (QCA) are an emerging computation technology in which basic states are represented by nanosize particles and logic operations are conducted through corresponding effects such as Coulomb interaction. This allows to overcome physical boundaries of conventional solutions such as CMOS and, hence, constitutes a promising direction for future computing devices. Despite these promises, however, the development of (automatic) design methods for QCAs is still in its infancy. In fact, QCA circuits are mainly designed manually thus far and only few heuristics are available. This frequently leads to unsatisfactory results and generally makes it hard to evaluate the quality of respective QCA designs. In this work, we propose an exact solution for the design of QCA circuits that can be configured e. g. to generate circuits that satisfy certain design objectives and/or physical constraints. For the first time, this allows for design exploration of QCA circuits. Experimental evaluations and case studies demonstrate the benefit of the proposed solution. Read more

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Synthesis of Approximate Coders for On-chip Interconnects Using Reversible Logic

Published in Design, Automation and Test in Europe, 2016

On-chip coding provides a remarkable potential to improve the energy efficiency of on-chip interconnects. However, the logic design of the encoder/decoder faces a main challenge: the area and power overhead should be minimal while, at the same time, decodability has to be guaranteed. To address these problems, we propose the concept of approximate coding, where the coding function is partially specified and the synthesis algorithm has a higher flexibility to simplify the circuit. Since conventional synthesis methods are unsuitable here, we propose an alternative synthesis approach based on reversible logic. Experimental evaluations confirm the benefits of both, the proposed concept of approximate codings as well as the proposed design method. Read more

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Look-ahead Schemes for Nearest Neighbor Optimization of 1D and 2D Quantum Circuits

Published in Asia and South Pacific Design Automation Conference, 2016

Ensuring nearest neighbor compliance of quantum circuits by inserting SWAP gates has heavily been considered in the past. Here, quantum gates are considered which work on non-adjacent qubits. SWAP gates are applied in order to “move” these qubits onto adjacent positions. However, a decision how exactly the SWAPs are “moved” has mainly been made without considering the effect a “movement” of qubits may have on the remaining circuit. In this work, we propose a methodology for nearest neighbor optimization which addresses this problem by means of a look-ahead scheme. To this end, two representative implementations are presented and discussed in detail. Experimental evaluations show that, in the best case, reductions in the number of SWAP gates of 56% (compared to the state-of-the-art methods) can be achieved following the proposed methodology. Read more

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