Conference and Journal Publications
You can also find my articles on my Google Scholar profile.
Published in Design, Automation and Test in Europe Conference, 2024
Recent advancements in Silicon Dangling Bond (SiDB) fabrication have transitioned from manual to automated processes. However, sub-nanometer substrate defects remain a significant challenge, thus preventing the fabrication of functional logic. Current design automation techniques lack defect-aware strategies. This paper introduces an idea for a surface defect model based on experimentally verified defects, which can be applied to enhance the robustness of established gate libraries. Additionally, a prototypical automatic placement and routing algorithm is presented, utilizing STM data from physical experiments to obtain dot-accurate circuitry resilient to atomic surface defects. Initial evaluations on surfaces with varying defect rates demonstrate their critical impact, suggesting that fabrication processes must achieve defect rates of around 0.1 % to further advance this circuit technology. Read more
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Published in Design, Automation and Test in Europe Conference, 2024
As Field-coupled Nanocomputing (FCN) gains traction as a viable post-CMOS technology, the EDA community lacks public benchmarks to evaluate the performance of academic and commercial design tools. We propose MNT Bench to address this gap by providing a platform for researchers to compare algorithms across a diverse set of benchmarks generated by multiple physical design tools. These benchmarks span various clocking schemes and gate libraries, with MNT Bench being consistently updated to integrate the latest advancements in the field. In fact, using MNT Bench, we were able to provide layouts that are substantially better (in terms of area) than everything the community generated thus far. Read more
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Published in Asia and South-Pacific Design Automation Conference, 2024
The Silicon Dangling Bond (SiDB) logic platform, an emerging computational beyond-CMOS nanotechnology, is a promising competitor due to its ability to achieve integration density and clock speed values that are several orders of magnitude higher compared to current CMOS fabrication nodes. However, the exact physical simulation of SiDB layouts, which is an essential component of any design validation workflow, is computationally expensive. In this paper, we propose a novel algorithm called QuickExact, which aims to be both, efficient and exact. To this end, we are introducing three techniques, namely 1) Physically-informed Search Space Pruning, 2) Partial Solution Caching, and 3) Effective State Enumeration. Extensive experimental evaluations confirm that, compared to the state-of-the-art algorithm, the resulting approach leads to a paramount runtime advantage of more than a factor of 5000 on randomly generated layouts and more than a factor of 2000 on an established gate library. Read more
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Published in International Symposium on Nanoscale Architectures, 2023
While conventional computing technologies reach their limits, the demand for computation power keeps growing, fueling the interest in post-CMOS technologies. One promising contestant in this domain is Field-coupled Nanocomputing (FCN), which conducts computations based on the repulsion of physical fields at the nanoscale. However, to realize a dedicated functionality in this technology design methods are needed that create corresponding FCN layouts. While several methods for FCN layout generation have been proposed in the past, the underlying complexity requires them to resort to heuristic approaches—leading to results of sub-par quality and offering room for improvement. In conventional CMOS design, post-layout optimization methods are available to exploit this potential for further improvement. Unfortunately, no such methods exists yet for FCN. In this work, we are addressing this gap and introduce the first post-layout optimization approach for FCN. Experimental evaluations show the benefits of the approach: Applied to layouts generated by two complementary state-of-the-art methods, the proposed post-layout optimization allows for a further area reduction of 50.79 % and 20.00 % on average, respectively—confirming the potential of post-layout optimization for FCN. Read more
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Published in International Symposium on Nanoscale Architectures, 2023
Silicon Dangling Bonds (SiDBs) constitute a beyond-CMOS computational nanotechnology platform that enables higher integration density and lower power consumption than contemporary CMOS nodes. Recent manufacturing breakthroughs in the domain sparked the interest of academia and industry alike in the race for a green computation future at the nanoscale. However, as the fabrication of SiDBs requires atomic precision, SiDB logic systems are inherently susceptible to environmental defects and material variations, which inevitably occur. The Operational Domain is a methodology to evaluate the resilience of SiDB logic against physical parameter variations. However, state-of-the-art implementations require a quadratic number of exponentially complex physical simulator calls to assess the operational domain. This paper presents two novel algorithms to obtain operational domains in an efficient fashion: one based on flood fill, and one based on contour tracing. Experimental evaluations confirm that they reduce the number of required simulator calls by 70.87 % and 95.29 %, respectively. Particularly contour tracing achieves the shift from a quadratic to a linear relation, thereby reducing the complexity and paving the way for realizing reliable SiDB-based computing systems. Read more
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Published in International Symposium on Nanoscale Architectures, 2023
Silicon Dangling Bonds (SiDBs) present a promising computational technology that goes beyond traditional CMOS. It enables the creation of circuitry using single atoms as elementary components. Since contemporary computational technologies approach their physical limits, SiDBs have attracted significant interest from both academia and industry. SiDBs allow for gate implementation of Boolean functions to realize arbitrary circuit logic. Hence, improvements at the gate level propagate through to the circuit level. Although fabrication capabilities are advancing rapidly and initial design automation methodologies have been proposed, the current design of SiDB gates is primarily based on manual labor. This paper presents an approach capable of designing SiDB gates using the minimum number of SiDBs possible for a given Boolean function, thus minimizing gate cost and providing an optimal basis for SiDB circuits. This methodology simplifies SiDB circuit designs and their corresponding manufacturing processes significantly, thereby accelerating the progress of this promising nanotechnology. Read more
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Published in Design Automation Conference, 2023
Recent breakthroughs in atomically precise manufacturing are paving the way for Field-coupled Nanocomputing (FCN) to become a real-world post-CMOS technology. This drives the need for efficient and scalable physical design automation methods. However, due to the problem’s NP-completeness, existing solutions either generate designs of high quality, but are not scalable, or generate designs in negligible time but of poor quality. In an attempt to balance scalability and quality, we created and evaluated a hybrid approach that combines the best of established design methods and deep reinforcement learning. This paper summarizes the obtained results. Read more
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Published in Design Automation Conference, 2023
Cryogenic CMOS circuits operate at temperatures close to absolute zero and are essential in many applications such as controllers for quantum computing but also medical engineering, space technology, or physical instruments. However, operating circuits at cryogenic temperatures fundamentally changes the underlying semiconductor physics that governs the CMOS transistor—rendering existing design automation approaches infeasible. In this work, we propose and implement the first end-to-end approach that enables design automation for cryogenic CMOS circuits. To this end, we (1) perform the first-of-its-kind measurements of commercial 5 nm FinFET transistors from 300 K down to 10 K, (2) use the results to validate and calibrate the first cryogenic-aware industrial-standard compact model for FinFET technology, (3) create cryogenic-aware standard cell libraries that are compatible with the existing EDA tool flows, and (4) propose an initial cryogenic-aware logic synthesis approach that re-uses established design automation expertise but optimizes it for cryogenic purposes. Evaluations, comparisons, and discussions of all these novel contributions confirm the applicability and validity of the resulting cryogenic-aware design automation flow. Read more
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Published in IEEE International Conference on Nanotechnology, 2023
With the ever-increasing demands of computing, post-CMOS technologies are sought after. Field-coupled Nanocomputing (FCN), which relies on physical field repulsion, is a class of technologies for energy-efficient computing. While the physical design for Quantum-dot Cellular Automata (QCA) has been researched for more than 20 years, the methodologies for its promising successor, namely Silicon Dangling Bonds (SiDBs), have yet to catch up. To prevent reinventing the wheel and utilizing the 20 years of development in QCA, this paper presents a methodology to create SiDB designs based on existing QCA design approaches by a 45° rotation, implemented as a remapping algorithm. The presented approach enables the direct translation of QCA layouts to SiDB ones with minimal overhead and allows to tap knowledge from decades of research. Read more
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Published in IEEE International Conference on Nanotechnology, 2023
Silicon Dangling Bonds (SiDBs) on the hydrogen-passivated silicon surface have emerged as a promising competitor in the realm of beyond-CMOS computational technologies. They have attracted the attention of academia and industry due to their greatly increased integration density and energy efficiency compared to contemporary fabrication nodes. Since information propagation and computation in the SiDB domain are based on electrostatic field coupling, SiDBs are considered as a room temperature-enabled technology. However, the effect of temperature on SiDB-based gates and their operation has not yet been considered. Consequently, established design automation flows and gate library proposals are temperature-agnostic without any guarantee of their operability in real-world scenarios. In this paper, we investigate for the first time the effect of temperature on the operation of SiDB-based gates. To this end, we utilize a newly developed temperature-aware simulator and exhaustively evaluate previously fabricated gates and theoretically proposed standard libraries. The results reveal significant temperature-sensitivity of many gates, highlighting the crucial role of considering temperature behavior in the realization of SiDB-based gates. Therefore, it is imperative to minimize the use of such temperature-sensitive components in future designs and to develop more robust standard gates. This research serves as the foundation for subsequent studies and is vital for the acceleration of the development of this promising green nanotechnology. Read more
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Published in IEEE International Conference on Nanotechnology, 2023
Silicon Dangling Bonds have established themselves as a promising competitor in the field of beyond-CMOS technologies. Their integration density and potential for energy dissipation advantages of several orders of magnitude over conventional circuit technologies sparked the interest of academia and industry alike. While fabrication capabilities advance rapidly and first design automation methodologies have been proposed, physical simulation effectiveness has yet to keep pace. Established algorithms in this domain suffer either from exponential runtime behavior or subpar accuracy levels. In this work, we propose a novel algorithm for the physical simulation of Silicon Dangling Bond systems based on statistical methods that offers both a time-to-solution and an accuracy advantage over the state of the art by more than one order of magnitude and a factor of more than three, respectively, as demonstrated by an exhaustive experimental evaluation. Read more
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Published in International Symposium on Nanoscale Architectures, 2022
The exponential growth of transistor density in integrated circuits is doomed to fail at the limits of physics in the foreseeable future. Quantum-dot Cellular Automata (QCA) is a post-CMOS contestant from the emerging Field-coupled Nanocomputing (FCN) paradigm which offers computations with tremendously low power dissipation. Recent physical accomplishments in this area also motivated the developments of corresponding design automation methods. However, although the higher integration density of QCA makes this technology a promising candidate for stacked, i.e. cuboid-like, chip architectures, all design automation solutions proposed thus far are limited to 2-dimensional architectures only. This work showcases the potential when the third dimension is additionally utilized. To this end, we must overcome certain obstacles for which corresponding solutions are proposed. Case studies on important regular structures such as bitwise AND/OR, binary adders, or multiplexers—for which we provide automatic generation scripts—confirm that exploiting the third dimension in this fashion yields a prodigious reduction in area occupation and cell count, differing by several orders of magnitude compared to the state of the art. Read more
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Published in International Symposium on Nanoscale Architectures, 2022
Establishing itself among the vanguard of beyond-CMOS candidates, Field-coupled Nanocomputing (FCN) has advanced in recent times due to fabrication breakthroughs of Silicon Dangling Bonds (SiDBs). At the foundation of these breakthroughs, experimental demonstrations showcase the feasibility of FCN logic components and wire segment implementations at the physical limits of scaling. However, automatic design methods for this highly-promising technology remain scarce, as they are impeded by the necessity to conform to particular constraints that differ from those in CMOS technologies. Previously proposed approaches are restricted by their inability to overcome scalability limitations and/or their failure to generate results of adequate quality. In this work, we aim to improve this state of the art %overcome the preceding techniques by addressing the epicenter of performance inadequacy and proposing a distinctive multi-path FCN routing algorithm that is explicitly adjusted to the design constraints dictated by FCN technologies. The resulting approach can be parameterized to generate signal routings for almost arbitrary FCN placements or, in case this is impossible, pinpoint the designer to the unsatisfied connections. Experimental evaluations confirm these abilities on an established benchmark set and demonstrate a runtime advantage of several orders of magnitude over a state-of-the-art physical design algorithm. Read more
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Published in Design Automation Conference, 2022
Field-coupled Nanocomputing (FCN) defines a class of post-CMOS nanotechnologies that promises compact layouts, low power operation, and high clock rates. Recent breakthroughs in the fabrication of Silicon Dangling Bonds (SiDBs) acting as quantum dots enabled the demonstration of a sub-30 nm2 OR gate and wire segments. This motivated the research community to invest manual labor in the design of additional gates and whole circuits which, however, is currently severely limited by scalability issues. In this work, these limitations are overcome by the introduction of a design automation framework that establishes a flexible topology based on hexagons as well as a corresponding Bestagon gate library for this technology and, additionally, provides automatic methods for physical design. By this, the first design automation solution for the promising SiDB platform is proposed. In an effort to support open research and open data, the resulting framework as well as all design and code files are made publicly available. Read more
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Published in Design & Test, 2022
This article proposes a complete 3-input gate library using atomic silicon quantum-dots made of silicon dangling bonds (SiDBs). This emerging technology aims to achieve ultra-low energy dissipation and high-density integration using field interactions rather than the flow of electric current. Our main contribution is a SiDB gate library of ten logic gates to cover all 256 3-input Boolean functions by utilizing NPN equivalence classes. Finally, the results present detailed properties of our designs and discuss their robustness against environmental variations. We use SiQAD, a state-of-art CAD tool specialized for SiDB technologies, for simulation and verification. Read more
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Published in Asia and South Pacific Design Automation Conference, 2021
This work was a Best Paper Award candidate at ASP-DAC 2021. Read more
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Published in International Conference on integrated Formal Methods, 2020
In the SMT(LRA) learning problem, the goal is to learn SMT(LRA) constraints from real-world data. To improve the scalability of SMT(LRA) learning, we present a novel approach called SHREC which uses hierarchical clustering to guide the search, thus reducing runtime. A designer can choose between higher quality (SHREC1) and lower runtime (SHREC2) according to their needs. Our experiments show a significant scalability improvement and only a negligible loss of accuracy compared to the current state-of-the-art. Read more
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Published in International Symposium On Leveraging Applications of Formal Methods, Verification and Validation, 2020
These days, robotic agents are finding their way into the personal environment of many people. With robotic vacuum cleaners commercially available already, comprehensive cognition-enabled agents assisting around the house autonomously are a highly relevant research topic. To execute these kinds of tasks in constantly changing environments, complex goal-driven control programs, so-called plans, are required. They incorporate perception, manipulation, and navigation capabilities among others. As with all technological innovation, consequently, safety and correctness concerns arise. Read more
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Published in Euromicro Conference on Digital System Design, 2020
Field-coupled Nanocomputing (FCN) is a computing concept with several promising post-CMOS candidate implementations that offer tremendously low power dissipation and highest processing performance at the same time. Two of the manifold physical implementations are Quantum-dot Cellular Automata (QCA) and Nanomagnet Logic (NML). Both inherently come with domain-specific properties and design constraints that render established conventional design algorithms inapplicable. Accordingly, dedicated design tools for those technologies are required. This paper provides an overview of two leading examples of such tools, namely fiction and ToPoliNano. Both tools provide effective methods that cover aspects such as placement, routing, clocking, design rule checking, verification, and logical as well as physical simulation. By this, both freely available tools provide platforms for future research in the FCN domain. Read more
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Published in Design Automation Conference, 2020
With the decline of Moore’s Law, several post-CMOS technologies are currently under heavy consideration. Promising candidates can be found in the class of Field-coupled Nanocomputing (FCN) devices as they allow for highest processing performance with tremendously low energy dissipation. With upcoming design automation in this domain, the need for formal verification approaches arises. Unfortunately, FCN circuits come with certain domain-specific properties that render conventional methods for the verification non-applicable. In this paper, we investigate this issue and propose a verification approach for FCN circuits that addresses this problem. For the first time, this provides researchers and engineers with an automatic method that allows them to check whether an obtained FCN circuit design indeed implements the given/desired function. A prototype implementation demonstrates the applicability of the proposed approach. Read more
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Published in IEEE Computer Society Annual Symposium on VLSI, 2020
This work won the Best Student Forum Paper Award at ISVLSI 2020. Read more
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Published in IEEE Computer Society Annual Symposium on VLSI, 2020
This work was a Best Paper Award candidate at ISVLSI 2020. Read more
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Published in Microprocessors and Microsystems: Embedded Hardware Design, 2020
Quantum-dot Cellular Automata (QCA) is an emerging nanotechnology with remarkable performance and energy efficiency. Computation and information transfer in QCA are based on field forces rather than electric currents. As a consequence, new strategies are required for design automation approaches in order to cope with the arising challenges. One of these challenges is the transport of information, which is affected by two particularities of the QCA technology. First, information flow in QCA is controlled by external clocks, and second, QCA is a planar technology in which gates, as well as interconnections, are mostly located in the same layer. The former demands proper synchronization already during the circuit design phase, while the latter results in high area costs for interconnections. This work focuses on both constraints and discusses its impact on the implementation of QCA circuits. Further, the concept of local and global synchronicity in QCA circuits is explored. The obtained results indicate that relaxing the global synchronicity constraint can reduce design size by about 70% while the throughput performance declines by similar values. Additionally, it can be shown that the impact of interconnections in QCA, like wires, fan-outs, and crossovers, is indeed substantial. That means, up to 75% of the total area is occupied by interconnections. Read more
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Published in Euromicro Conference on Digital System Design, 2019
In this paper, we propose the first approach for verifying plans of cognition-enabled autonomous robots that perform everyday manipulation activities in human environments. Our methodology is based on the new Intermediate Plan Verification Language (IPVL) which is used to represent plans, environments, and robot belief states in one joint formal model. We devise a symbolic execution engine for IPVL and show the effectiveness of our overall verification methodology in a case study. Read more
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Published in IEEE Computer Society Annual Symposium on VLSI, 2019
Field-Coupled Nanocomputing (FCN) allows for conducting computations with a power consumption that is magnitudes below current CMOS technologies. Recent physical implementations confirmed these prospects and put pressure on the Electronic Design Automation (EDA) community to develop physical design methods comparable to those available for conventional circuits. While the major design task boils down to a place and route problem, certain characteristics of FCN circuits introduce further challenges in terms of dedicated clock arrangements which lead to rather cumbersome clocking constraints. Thus far, those constraints have been addressed in a rather unsatisfactory fashion only. Read more
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Published in International Workshop on Logic & Synthesis, 2019
As a class of emerging post-CMOS technologies, Field-coupled Nanocomputing (FCN) devices promise computation with tremendously low energy dissipation. Even though ground breaking advances in several physical implementations like Quantum-dot Cellular Automata (QCA) or Nanomagnet Logic (NML) have been made in the last couple of years, design automation for FCN is still in its infancy and often still relies on manual labor. In this paper, we present an open source framework called fiction for physical design and technology mapping of FCN circuits. Its efficient data structures, state-of-the-art algorithms, and extensibility provide a basis for future research in the community. Read more
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Published in ACM Journal on Emerging Technologies in Computing Systems, 2019
Field-coupled Nanocomputing (FCN) technologies provide an alternative to conventional CMOS-based computation technologies and are characterized by intriguingly low energy dissipation. Accordingly, their design received significant attention in the recent past. FCN circuit implementations like Quantum-dot Cellular Automata (QCA) or Nanomagnet Logic (NML) have already been built in labs and basic operations such as inverters, Majority, AND, OR, etc. are already available. The design problem basically boils down to the question how to place basic operations and route their connections so that the desired function results while, at the same time, further constraints (related to timing, clocking, path lengths, etc.) are satisfied. While several solutions for this problem have been proposed, interestingly no clear understanding about the complexity of the underlying task exists thus far. In this research note, we consider this problem and eventually prove that placement and routing for tile-based FCN circuits is NP-complete. By this, we provide a theoretical foundation for the further development of corresponding design methods. Read more
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Published in Asia and South Pacific Design Automation Conference, 2019
Field-coupled Nanocomputing (FCN) technologies are considered as a solution to overcome physical boundaries of conventional CMOS approaches. But despite ground breaking advances regarding their physical implementation as e. g. Quantumdot Cellular Automata (QCA), Nanomagnet Logic (NML), and many more, there is an unsettling lack of methods for large-scale design automation of FCN circuits. In fact, design automation for this class of technologies still is in its infancy – heavily relying either on manual labor or automatic methods which are applicable for rather small functionality only. This work presents a design method which – for the first time – allows for the scalable design of FCN circuits that satisfy dedicated constraints of these technologies. The proposed scheme is capable of handling around 40000 gates within seconds while the current state-of-the-art takes hours to handle around 20 gates. This is confirmed by experimental results on the layout level for various established benchmarks libraries. Read more
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Published in Euromicro Conference on Digital System Design, 2018
Quantum-Dot Cellular Automata (QCA) are an emerging nanotechnology with remarkable performance and energy efficiency. Computation and information transfer in QCA is based on field forces rather than electric currents. As a consequence, new strategies are required for design automation approaches in order to cope with the arising challenges. One of these challenges rises from the fact that QCA is a planar technology. That means, logic gates as well as interconnection elements are mostly located in the same layer. Hence, it is expected that interconnections have higher influence on the final design costs than in conventional integrated technologies. For the first time, this paper presents an extensive study on the quantification of this impact. Therefore, we consider the entire design flow for QCA circuits from the initial synthesis (using different synthesis approaches) to the corresponding placement on a QCA grid. Then, we characterize the respectively obtained QCA circuits in terms of area, delay and energy costs. The obtained results indicate that the impact of interconnections in QCA is indeed substantial. Design costs including or not including interconnections differ by several orders of magnitudes, which motivates to completely re-think how logic synthesis for QCA circuits shall be conducted in the future. Read more
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Published in IEEE International Conference on Nanotechnology, 2018
Proper synchronization in clocked Field-Coupled Nanocomputing (FCN) circuits is a fundamental problem. In this work, we show for the first time that global synchronicity is not a mandatory requirement in clocked FCN designs and discuss the considerable restrictions that global synchronicity presents for sequential and large-scale designs. Furthermore, we propose a solution that circumvents design restrictions due to synchronization requirements and present a novel RS-latch. Read more
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Published in Design, Automation and Test in Europe, 2018
Quantum-dot Cellular Automata (QCA) are an emerging computation technology in which basic states are represented by nanosize particles and logic operations are conducted through corresponding effects such as Coulomb interaction. This allows to overcome physical boundaries of conventional solutions such as CMOS and, hence, constitutes a promising direction for future computing devices. Despite these promises, however, the development of (automatic) design methods for QCAs is still in its infancy. In fact, QCA circuits are mainly designed manually thus far and only few heuristics are available. This frequently leads to unsatisfactory results and generally makes it hard to evaluate the quality of respective QCA designs. In this work, we propose an exact solution for the design of QCA circuits that can be configured e. g. to generate circuits that satisfy certain design objectives and/or physical constraints. For the first time, this allows for design exploration of QCA circuits. Experimental evaluations and case studies demonstrate the benefit of the proposed solution. Read more
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Published in Design, Automation and Test in Europe, 2016
On-chip coding provides a remarkable potential to improve the energy efficiency of on-chip interconnects. However, the logic design of the encoder/decoder faces a main challenge: the area and power overhead should be minimal while, at the same time, decodability has to be guaranteed. To address these problems, we propose the concept of approximate coding, where the coding function is partially specified and the synthesis algorithm has a higher flexibility to simplify the circuit. Since conventional synthesis methods are unsuitable here, we propose an alternative synthesis approach based on reversible logic. Experimental evaluations confirm the benefits of both, the proposed concept of approximate codings as well as the proposed design method. Read more
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Published in Asia and South Pacific Design Automation Conference, 2016
Ensuring nearest neighbor compliance of quantum circuits by inserting SWAP gates has heavily been considered in the past. Here, quantum gates are considered which work on non-adjacent qubits. SWAP gates are applied in order to “move” these qubits onto adjacent positions. However, a decision how exactly the SWAPs are “moved” has mainly been made without considering the effect a “movement” of qubits may have on the remaining circuit. In this work, we propose a methodology for nearest neighbor optimization which addresses this problem by means of a look-ahead scheme. To this end, two representative implementations are presented and discussed in detail. Experimental evaluations show that, in the best case, reductions in the number of SWAP gates of 56% (compared to the state-of-the-art methods) can be achieved following the proposed methodology. Read more
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