Building a Machine Learning Accelerator with Silicon Dangling Bonds: From Verilog to Quantum Dot Layout

At a time when traditional CMOS technologies approach their fundamental scaling limits and artificial intelligence continues to escalate global computational demands, emerging post-CMOS technologies like Silicon Dangling Bonds (SiDBs) provide promising pathways towards energy-efficient computation. SiDBs offer atomic-scale precision and discrete charge control, enabling the realization of ultra-dense computational logic. However, manual layout design and verification have historically restricted the exploration and scalability of SiDB-based logic systems. To this end, this work demonstrates an automated, end-to-end Electronic Design Automation (EDA) flow for designing and synthesizing a core component of a Matrix Multiply Unit (MXU) from high-level Register-transfer Level (RTL) Verilog descriptions down to dot-accurate SiDB layouts. Leveraging recent advances in SiDB-focused EDA tooling, we demonstrate the first fully automated design flow capable of translating RTL descriptions into manufacturable quantum-dot layouts. The proposed hierarchical Verilog approach addresses existing EDA constraints while facilitating comprehensive operational verification via test benches. Additionally, our design process incorporates reliability-focused Figures Of Merit (FoMs), ensuring the selection of robust logic gates throughout synthesis. Our synthesized MXU Processing Element (PE) layout represents a significant milestone in SiDB logic design, bridging previously manually-intensive workflows with scalable, automated methodologies. Despite achieving larger footprints than hand-crafted designs, the presented approach provides a valuable foundation for future optimization and widespread adoption of SiDB-based computing architectures.

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