Invited Talks

aigverse: Toward Machine Learning-Driven Logic Synthesis

July 02, 2025

Invited Talk, Free Silicon Conference, Frankfurt (Oder), Germany

The integration of machine learning into logic synthesis has long lagged behind, hampered by a fundamental conceptual divide. Logic synthesis demands mathematical precision and guarantees of functional correctness, while machine learning embraces probabilistic reasoning and statistical generalization. This contrast is further exacerbated by a practical ecosystem mismatch: high-performance logic synthesis tools are typically implemented in C/C++, whereas the machine learning community predominantly operates in Python.

Chip Design for AI

June 13, 2025

Workshop with Hands-on, 4th Annual Hack4Her Event, Amsterdam, Netherlands

Machine Learning and Artificial Intelligence are the defining technologies of this decade. However, training and running state-of-the-art models require significant computational power, typically provided by large GPU clusters. One promising solution is the development of Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs), which are custom hardware designed to accelerate specific applications. In this workshop, attendees learned about the logic synthesis and physical design processes used to create ASIC layouts and FPGA designs from specifications. They applied these techniques to generate custom machine-learning accelerators and inference engines ready for tape-out. The workshop includes a hands-on session for practical experience.

The Munich Nanotech Toolkit (MNT)

February 19, 2025

Invited Workshop Contribution, Universidade Federal de Minas Gerais - Workshop on Nanocomputing, Belo Horizonte, Brazil

As traditional CMOS technology approaches its fundamental limits, the focus shifts towards beyond-CMOS paradigms like Field-coupled Nanocomputing (FCN). Recent breakthroughs in atom-scale fabrication, particularly with Silicon Dangling Bonds (SiDBs), have demonstrated the potential of FCN but also revealed significant design challenges absent in conventional electronics. Dominated by wiring costs and constrained by strict planarity and complex clocking requirements, FCN demands entirely new design automation approaches.

Logic Synthesis for AI

June 09, 2024

Workshop with Hands-on, 3rd Annual Hack4Her Event, Amsterdam, Netherlands

Machine Learning and Artificial Intelligence are the defining technologies of this decade. However, training and running state-of-the-art models require significant computational power, typically provided by large GPU clusters. One promising solution is the development of Application-Specific Integrated Circuits (ASICs) and Field-Programmable Gate Arrays (FPGAs), which are custom hardware designed to accelerate specific applications. In this workshop, attendees learned about the logic synthesis and physical design processes used to create ASIC layouts and FPGA designs from specifications. They applied these techniques to generate custom machine-learning accelerators and inference engines ready for tape-out. The workshop includes a hands-on session for practical experience.

The Case for Planar Logic Synthesis - Crossing Costs in Nanotech

June 06, 2024

Invited Special Session, International Workshop on Logic and Synthesis (IWLS) 2024, Zurich, Switzerland

In recent years, the field of logic synthesis for beyond-CMOS technologies has seen significant changes, revealing new cost functions and constraints that challenge traditional assumptions. In some implementations, splitters and buffers are essential for path balancing. However, recent advancements in fabrication and physical simulation of certain computational nanotechnologies revealed the necessity for 100% planar networks. This unconventional cost metric creates a new playground for innovation in logic synthesis.

The Munich Nanotech Toolkit (MNT)

March 11, 2024

Guest Researcher Lecture, Department of Physics - Condensed Matter, University of Alberta, Edmonton, Canada

As traditional CMOS technology approaches its fundamental limits, the focus shifts towards beyond-CMOS paradigms like Field-coupled Nanocomputing (FCN). Recent breakthroughs in atom-scale fabrication, particularly with Silicon Dangling Bonds (SiDBs), have demonstrated the potential of FCN but also revealed significant design challenges absent in conventional electronics. Dominated by wiring costs and constrained by strict planarity and complex clocking requirements, FCN demands entirely new design automation approaches.

Design Automation for Field-coupled Nanotechnologies

May 11, 2021

Thesis overview, École polytechnique fédérale de Lausanne - Laboratoire des Systèmes Intégrés, Lausanne, Switzerland

In this invited talk in the Laboratoire des Systèmes Intégrés (LSI) at the École polytechnique fédérale de Lausanne (EPFL) in Switzerland, I gave an overview of my dissertation entitled Design Automation for Field-coupled Nanotechnologies. Due to the brevity of this 40 minute talk, I focused on an excerpt of my work, namely placement & routing for FCN. The discussed algorithms allow for the generation of circuit layouts from given logic networks in both exact and scalable fashion.

Field-coupled Nanocomputing (FCN)

January 16, 2019

Lecture, Johannes Kepler University Linz - Emerging Computer Technologies, Linz, Austria

In this guest lecture in the graduate course Emerging Computer Technologies at Johannes Kepler University Linz, I gave an introduction to Field-coupled Nanocomputing (FCN) technologies and concepts. This promising class of post-CMOS devices has the potential for highest processing performance with tremendously low energy dissipation. At the same time, physical design of these nano-structures imposes hard challenges, even compared to classical CMOS layout.

Marcel Walter

Invited Talks