The Case for Planar Logic Synthesis - Crossing Costs in Nanotech

In recent years, the field of logic synthesis for beyond-CMOS technologies has seen significant changes, revealing new cost functions and constraints that challenge traditional assumptions. In some implementations, splitters and buffers are essential for path balancing. However, recent advancements in fabrication and physical simulation of certain computational nanotechnologies revealed the necessity for 100% planar networks. This unconventional cost metric creates a new playground for innovation in logic synthesis.

This special session provided a physical background on why wire crossings are infeasible in computational nanotechnologies, and presented initial strategies for crossing mitigation and legalization. Most importantly, it serves as a call to the logic synthesis community to participate in this exciting new field.