aigverse: A Unified Infrastructure for Machine Learning-Driven Logic Synthesis
Published in Asia and South Pacific Design Automation Conference (ASP-DAC), 2027
Recommended citation: Marcel Walter, Isabella Venancia Gardner, and Robert Wille. Asia and South Pacific Design Automation Conference (ASP-DAC), 2027. https://marcelwa.github.io/files/2027_001.pdf
The rapid advancement of Machine Learning (ML) has demonstrated immense potential for logic synthesis, design-space exploration, and circuit optimization. In practice, however, researchers who want to combine these areas repeatedly face the same infrastructure problem: the surrounding ML and data-science ecosystem is centered on Python, whereas the core data structures and algorithms of logic synthesis are the product of decades of highly optimized C/C++ engineering. Connecting these environments often requires project-specific circuit conversions, tool orchestration, and data-preparation code. To address this recurring gap, this paper introduces aigverse, a unified open-source infrastructure project that brings mature logic synthesis capabilities into Python-first workflows without reimplementing them there. To this end, aigverse offers direct bindings to high-performance C/C++ synthesis libraries through an idiomatic Python interface. It provides reusable support for circuit construction and manipulation, benchmark access and dataset generation, optimization and equivalence-checking flows, and export into graph and tensor representations for downstream data science and ML pipelines. In a case study comparing a pure-Python tensorization pipeline from the literature against aigverse, the latter achieves up to 17.2× faster end-to-end tensorization while reducing isolated framework hand-off overhead by three to four orders of magnitude depending on circuit size.
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