Toward Compact Planar Circuits for Atomic-Scale Computing: A Hybrid Crossing Elimination Flow

The growing computational demands of artificial intelligence challenge the continued scaling of conventional CMOS technology, motivating the exploration of alternative paradigms such as Atomic-Scale Computing. Among potential implementations, Field-Coupled Nanocomputing (FCN) is a promising candidate that transmits information through electric or magnetic field interactions rather than current flow, enabling extremely dense circuits with potentially terahertz operating frequencies. However, FCN circuits are implemented on a single physical layer where logic gates and interconnects share the same structures. Consequently, signal crossings pose a major challenge, since proposed wire-crossing structures are not sufficiently reliable for physically realizable layouts. Previous work addresses this by performing planarization—i.e., eliminating crossings—during logic synthesis via node duplication to provide planar networks for placement and routing. However, this approach suffers from poor scalability and neglects necessary preprocessing steps required for valid FCN logic networks. In this work, we propose a planar FCN synthesis flow that improves the interaction between preprocessing steps for FCN logic networks and planarization. Furthermore, we introduce a hybrid crossing elimination strategy that resolves intersections through either node duplication or equivalent logical structures that emulate signal crossings, thereby bypassing the need for physical crossing gates. Experimental results demonstrate significant reductions in network size, achieving an average reduction of 34.65 %, and up to 97.71 % for circuits where node duplication exhibits particularly poor scalability, enabling more compact planar circuits suitable for subsequent placement and routing.

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