Minimizing Area and Delay in Planar Physical Design for Field-coupled Nanocomputing

Field-coupled Nanocomputing (FCN) is a promising post-CMOS technology that transmits information via electric or magnetic fields rather than current flow. It uses nanoscale cells to implement logic gates and interconnects, enabling minimal circuit footprints and high computational density. These properties make FCN well-suited for future high-performance applications such as artificial intelligence and scientific computing. Unlike CMOS, FCN circuits are constrained to a single physical layer, requiring logic and interconnects to coexist in the same plane. In FCN layouts, wire crossings are commonly used to route intersecting signals. However, experimental and simulation studies have shown that such crossings degrade signal stability and reliability, making them unsuitable for practical FCN designs. As a result, planar layouts that completely avoid wire crossings are a strict requirement for reliable circuit implementation. This work presents a placement and routing algorithm that generates fully planar FCN layouts while optimizing both area and delay. In contrast to the current state-of-the-art planar physical design flow, which relies on greedy heuristics, our method performs placement and routing in a level-by-level manner, effectively minimizing wiring overhead within each level. Experimental results demonstrate that our approach achieves an average reduction of 21.09 % in layout area and 15.24 % in delay, providing a scalable and efficient solution for practical FCN circuit implementation.

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