Holistic Physical Design for Silicon Atomic Logic: Cramming More Components onto Clock Zones

Field-Coupled Nanocomputing (FCN) presents an exciting foundation for post-CMOS computing, and among its variants, Silicon Dangling Bond (SiDB) logic shows particular promise. Building on this technology, recent work has established an end-to-end design flow that synthesizes SiDB circuits directly from logic-level specifications. These circuits rely on an FCN clocking scheme to ensure directional and stable computation across sequences of logic gates. This clocking mechanism is indispensable: it actively nullifies parasitic interactions—or crosstalk—that arise when multiple gates are placed in close proximity, a fundamental concern in FCN-based circuits. However, a curious mismatch arises: while logic gates in SiDB can be implemented at the atomic scale, the metal pitches used to generate the clock signal remain relatively coarse. As a result, the nanoscopic SiDB logic gates must be artifically enlarged to fit one gate per clock zone, simply to interface with the clocking infrastructure. This approach, though functional, squanders the incredible density potential of atom-scale SiDB logic. To unlock that potential, we advocate for a holistic gate design methodology: crafting entire multi-gate assemblies that are small enough to fit into a single clock zone, while simultaneously mastering the delicate crosstalk interactions that such compactness entails. Yet, this compact design challenge gives rise to a monstrous design space. The number of possible combinations grows exponentially in the number of gates, with the number of distinct gate implementations as base—of which there are many thousands. Each candidate solution must be evaluated using physical simulation across all input combinations, which itself scales exponentially with the number of SiDBs in the design. As a result, design automation efforts to date have favored simpler, more sparse circuit topologies to preserve tractability—at the expense of logic density. In this work, we confront the challenge head-on. With an experimental evaluation, it is shown that the proposed methodology enables cramming significantly more logic into each clock zone of an SiDB circuit—advancing toward a truly holistic physical design flow for atomic-scale logic.

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