A Framework for Post-Mapping Feedback-Guided Selective Logic Transformations

Modern logic synthesis flows optimize proxy metrics, such as node count or depth, at the technology-independent level to indirectly improve area and delay. However, optimal values of proxy metrics do not necessarily translate to optimal post-mapping quality. With rising wafer costs at advanced technology nodes, area minimization becomes increasingly important, motivating the use of higher-effort optimization techniques. To address this development, we propose such a framework that leverages post-mapping information to guide technology-aware transformations, informed by feedback from the technology-mapping stage. Exemplarily applied to area-driven rewriting, the method achieves an average post-mapping area improvement of 0.72 % after a single iteration. The maximum gain is 6.3 %, with a strong effect size (r = 0.9167), at the cost of a runtime overhead of 274 %. Nevertheless, the method remains scalable even for very large circuits and is generically applicable to most optimization algorithms and objectives, such as post-mapping area and delay. However, these improvements do not consistently accumulate over multiple iterations. Nevertheless, the results demonstrate that, in the single-iteration case, feedback-guided transformations can improve technology-specific outcomes, even though they would be considered suboptimal by conventional proxy metrics. The proposed framework remains preliminary: it is at this moment still susceptible to becoming trapped in local minima and may exhibit instability due to uncertainties in selecting the correct transformation steps. While it is currently limited to discarding non-beneficial transformations exclusively, future work will explore enabling the discovery of new optimization opportunities to increase applicability.