BitPlanarNet: Learning-to-Layout Planar Gate Networks for Emerging Devices

Emerging planar computing platforms such as atomic-scale computing and silicon photonics combine gates and interconnects in a single 2D plane, making wiring and crossings dominant bottlenecks. This work reframes differentiable logic network training as one-pass synthesis: BitPlanarNet trains a strictly planar gate network that maps one-to-one to device primitives. Building on differentiable logic gate networks (DLGNs), each neuron selects a 2-input/2-output primitive and connects only to nearest neighbors, yielding a gate-level layout at discretization. It is demonstrated that this concept is physically viable by successfully fabricating a 33 × 25 nm2 representative learned dangling-bond logic layout on a hydrogen-passivated silicon surface using a scanning tunneling microscope. On image-classification tasks, BitPlanarNet achieves accuracy comparable to unconstrained DLGNs—remaining within approximately 1 percentage point on MNIST and 5 percentage points on CIFAR-10—while guaranteeing planar connectivity, providing a versatile methodology for translating learned tasks directly into realizable gate layouts on emerging planar technologies.

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